PRELIMINARY TECHNICAL DATA

a

12-Bit, 170 MSPS

3.3V A/D Converter

Preliminary Technical Data

AD9430

FEATURES

SNR = 65dB @ Fin up to 65MHz at 170Msps

Excellent Linearity:

- DNL = +/- 1 lsb (typ)

- INL = +/- 1.5 lsb (typ)

Two Output Data options

- Demultiplexed 3.3V CMOS outputs each at 85 Msps

- LVDS at 170Msps

700 MHz Full Power Analog Bandwidth

On–chip reference and track/hol d

Power dissipation = 1.25W typical at 170Msps

1.5V Input voltage range

+3.3V Supply Operation

Output data format option

Data Sync input and Data Clock output provided

Interleaved or parallel data output option (CMOS)

Clock Duty Cycle Stabilizer.

APPLICATIONS

Wireless and Wired Broadband Communications

-

Wideband carrier frequency systems

-

Cable Reverse Path

Communications Test Equipment

Radar and Satellite sub-systems

Power Amplifier Linearization

PRODUCT DESCRIPTION

The AD9430 is a 12-bit monolithic sampling analog–to–

digital converter with an on–chip track–and–hold circuit and

is optimized for low cost, low power, small size and ease of

use. The product operates up to 170 Msps conversion rate

and is optimized for outstanding dynamic performance in

wideband carrier systems.

The ADC requires a +3.3V power supply and a differential

encode clock for full performance operation. No external

reference or driver components are required for many

applications. The digital outputs are TTL/CMOS or LVDS

compatible. Separate output power supply pins support

interfacing with 3.3V CMOS logic.

An output data format select option of two’s complement or

offset binary is supported. In CMOS mode two output buses

support demultiplexed data up to 85 Msps rates. A data sync

input is supported for proper output data port alignment and

a data clock output is available for proper output data timing.

Fabricated on an advanced BiCMOS process, the AD9430 is

available in a 100 pin surface mount plastic package (100

TQFP ePAD) specified over the industrial temperature range

(–40°C to +85°C).

LVDS

Outputs

CMOS

Outputs

S2

DS-

DS+

Data(24), OR(2)

12

Scaleable

Reference

ADC

12-bit

Pipeline

Core

Track &

Hold

Clock

Management

AIN+

AIN-

ENC+

ENC-

S4

SENSE

VREF

DrGND

AGND

AD9430

S1

S5

DCO-

DCO+

A port

B port

Data(12), OR(1)

Data(12), OR(1)

Select CMOS or LVDS

AD9430 FUNCTIONAL BLOCK DIAGRAM

REV. PrG 4/01/2002

Information furnished by Analog Devices is believed to be accurate and

reliable.However,no responsibility is assumed by Analog Devices for its use,nor

for any infringements of patents or other rights of third parties that may result from

its use.No license is granted by implication or otherwise under any patent or

patent rights of Analog Devices.

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Tel:781/329-4700

www.analog.com

Fax:781/326-8703

© Analog Devices, Inc., 2002