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AD9873JS 数据表(PDF) 5 Page - Analog Devices

部件名 AD9873JS
功能描述  Analog Front End Converter for Set-Top Box, Cable Modem
PDF  39 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD9873JS 数据表(HTML) 5 Page - Analog Devices

  AD9873JS Datasheet HTML 1Page - Analog Devices AD9873JS Datasheet HTML 2Page - Analog Devices AD9873JS Datasheet HTML 3Page - Analog Devices AD9873JS Datasheet HTML 4Page - Analog Devices AD9873JS Datasheet HTML 5Page - Analog Devices AD9873JS Datasheet HTML 6Page - Analog Devices AD9873JS Datasheet HTML 7Page - Analog Devices AD9873JS Datasheet HTML 8Page - Analog Devices AD9873JS Datasheet HTML 9Page - Analog Devices Next Button
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REV. 0
–5–
AD9873
Test
Parameter
Temp
Level
Min
Typ
Max
Unit
12-BIT ADC CHARACTERISTICS (Continued)
Dynamic Performance (AIN = –0.5 dB FS, f = 5 MHz)
Signal-to-Noise and Distortion Ratio (SINAD)
Full
III
62.3
65
dB
Signal-to-Noise and Distortion Ratio (SINAD)
3
Full
IV
67.4
dB
Effective Number of Bits (ENOB)
Full
III
10.0
10.5
Bits
Effective Number of Bits (ENOB)
3
Full
IV
10.8
Bits
Signal-to-Noise Ratio (SNR)
Full
III
63.3
65.3
dB
Signal-to-Noise Ratio (SNR)
3
Full
IV
67.4
dB
Total Harmonic Distortion (THD)
Full
III
–77.6
–65.4
dB
Total Harmonic Distortion (THD)
3
Full
IV
–77.6
dB
Spurious Free Dynamic Range (SFDR)
Full
III
65.7
80
dB
Spurious Free Dynamic Range (SFDR)
3
Full
IV
80
dB
Differential Phase
25 C
IV
<0.1
Degree
Differential Gain
25 C
IV
<1
LSB
VIDEO CLAMP INPUT
Input Voltage Range
Full
IV
2
V
Clamp Current Positive
25 C
IV
1.3
mA
Clamp Droop Current
25 CIV
2
A
Clamp Level Offset Programming Range
25 C
III
256
512
2032
LSB
Clamp Level Resolution
25 C
IV
16
LSB
Carrier Rejection Filter Bandwidth (–3 dB)
25 C
IV
0.6
MHz
Dynamic Performance (AIN = –0.5 dB FS, f = 5 MHz)
Signal-to-Noise and Distortion Ratio (SINAD)
Full
IV
52
dB
Effective Number of Bits (ENOB)
Full
IV
8.34
Bits
Signal-to-Noise Ratio (SNR)
Full
IV
61.0
dB
Total Harmonic Distortion (THD)
Full
IV
–53.0
dB
Spurious Free Dynamic Range (SFDR)
Full
IV
55.0
dB
Differential Phase
25
°C
IV
<0.1
Degree
Differential Gain
25
°C
IV
<8
LSB
CHANNEL-TO-CHANNEL ISOLATION
Tx DAC-to-ADC Isolation
(5 MHz Analog Output)
Isolation Between Tx and 8-Bit ADCs
25 C
IV
>80
dB
Isolation Between Tx and 10-Bit ADC
25 C
IV
>85
dB
Isolation Between Tx and 12-Bit ADC
25 C
IV
>90
dB
ADC-to-ADC Isolation
(AIN = –0.5 dB FS, f = 5 MHz)
Isolation Between IF12 and Video
25 C
III
70
>70
dB
Isolation Between IF10 and IF12
25 C
IV
>80
dB
Isolation Between Q in and IF10
25 C
IV
>80
dB
Isolation Between Q in and I Inputs
25 C
IV
>70
dB
TIMING CHARACTERISTICS (20 pF Load)
Wake-Up Time
N/A
N/A
200
tMCLK Cycles
Minimum RESET Pulsewidth Low (tRL)
N/A
N/A
5
tMCLK Cycles
Digital Output Rise/Fall Time
25 C
III
2.8
4
ns
Tx/Rx Interface
MCLK Frequency (fMCLK)25 C
III
66
MHz
TxSYNC/TxIQ Set Up Time (tSU)25 C
III
3
ns
TxSYNC/TxIQ Hold Time (tHD)25 C
III
3
ns
RxSYNC/RxIQ/IF to Valid Time (tTV)25 C
III
5.2
ns
RxSYNC/RxIQ/IF Hold Time (tHT)25 C
III
0.2
ns
Serial Control Bus
SCLK Frequency (fSCLK)
Full
III
15
MHz
Clock Pulsewidth High (tPWH)
Full
III
30
ns
Clock Pulsewidth Low (tPWL)
Full
III
30
ns
Clock Rise/Fall Time
Full
III
1
ms
Data/Chip-Select Setup Time (tDS)
Full
III
25
ns
Data Hold Time (tDH)
Full
III
0
ns
Data Valid Time (tDV)
Full
III
30
ns



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