AD9873JS datasheet(6/39 Pages) AD

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AD9873–SPECIFICATIONS

Test

Parameter

Temp

Level

Min

Typ

Max

Unit

CMOS LOGIC INPUTS

Logic “1” Voltage

25 C

III

2.0

Logic “0” Voltage

25 C

III

0.8

Logic “1” Current

25 C

III

Logic “0” Current

25 C

III

Input Capacitance

25 CIV

CMOS LOGIC OUTPUTS (1 mA Load)

Logic “1” Voltage

25 C

III

2.4

Logic “0” Voltage

25 C

III

0.4

POWER SUPPLY

Analog Supply Current IAS

25 C

115

Digital Supply Current IDS

Full Operating Conditions

4 (Register 02h = 00h)

25 C

250

Zero Input Tx

4 (Register 02h = 00h)

25 C

175

205

25% Tx Burst Duty Cycle4 (Register 02h = 00h)

25 C

210

Power-Down Digital Tx (Register 02h = 20h)

°CII

Power Supply Rejection (Differential Signal)

Tx DAC

25 C

<0.25

% FS

8-Bit ADC

25 C

<0.004

% FS

10-Bit ADC

25 C

<0.002

% FS

12-Bit ADC

25 C

<0.0004

% FS

NOTES

1Single tone generated by applying a 1.6875 MHz sine signal to the Q Channel and the 90 degree phase shifted (cosine) signal to the I Channel.

2Sampling directly with f

OSCCIN/2. No degradation due to Clock Multiplier PLL. ADC Clock Select Register 08h, Bits 5 and 7 set to “1.”

3Sampling directly with f

OSCCIN. No degradation due to Clock Multiplier PLL. ADC Clock Select Register 08h, Bits 5 and 7 set to “1.”

4See performance graph TPC 2 for power saving in burst mode operation.

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