AD9873JS datasheet(30/39 Pages) AD

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REV. 0

AD9873

–30–

RECEIVE PATH (Rx)

ADC Theory of Operation

The AD9873’s analog-to-digital converters implement pipelined

multistage architectures to achieve high sample rates while con-

suming low power. Each ADC distributes the conversion over

several smaller ADC subblocks, refining the conversion with

progressively higher accuracy as it passes the results from stage

to stage. As a consequence of the distributed conversion, ADCs

require a small fraction of the 2

N comparators used in a traditional

n-bit flash-type ADC. A sample-and-hold function within each

of the stages permits the first stage to operate on a new input

sample while the remaining stages operate on preceding samples.

Each stage of the pipeline, excluding the last, consists of a low

resolution flash ADC connected to a switched capacitor DAC and

interstage residue amplifier (MDAC). The residue amplifier

amplifies the difference between the reconstructed DAC output

and the flash input for the next stage in the pipeline. One bit of

redundancy is used in each one of the stages to facilitate digital

correction of flash errors. The last stage simply consists of a

flash ADC.

D/A

A/D

SHA

CORRECTION LOGIC

D/A

A/D

SHA

GAIN

AINP

AINN

AD9873

Figure 17. ADC Architecture

The analog inputs of the AD9873 incorporate a novel structure

that merges the input sample and hold amplifiers (SHA), and

the first pipeline residue amplifiers into single, compact switched-

capacitor circuits. This structure achieves considerable noise

and power savings over a conventional implementation that uses

separate amplifiers by eliminating one amplifier in the pipeline. By

matching the sampling network of the input SHA with the first

stage flash ADC, the ADCs can sample inputs well beyond the

Nyquist frequency with no degradation in performance.

The digital data outputs of the ADCs are represented in straight

binary format. They saturate to full scale or zero when the input

signal exceeds the input voltage range.

Receive Timing

The AD9873 sends multiplexed data to the Rx IQ and IF out-

puts on every rising edge of MCLK. Rx SYNC frames the start

of each Rx IQ data Symbol. Both 8-bit ADCs transfer their data

within four MCLK cycles using 4-bit data packages (I MSB,

I LSB, Q MSB and Q LSB). 10-bit and 12-bit ADCs are com-

pletely read on every second MCLK cycle. Rx SYNC is high for

every second 10-bit ADC data (if 8-bit ADC is not in power-

down mode).

Driving the Analog Inputs

Figure 19 illustrates the equivalent analog inputs of the AD9873,

(a switched capacitor input). Bringing CLK to a logic high,

opens Switch 3 and closes Switches S1 and S2. The input source is

connected to AIN and must charge capacitor CH during this time.

Bringing CLK to a logic low opens S2, and then Switch 1 opens

followed by closing S3. This puts the input in the hold mode.

AINP

AINN

VBIAS

AD9873

Figure 19. Differential Input Architecture

The structure of the input SHA places certain requirements on

the input drive source. The combination of the pin capacitance,

and the hold capacitance, CH, is typically less than 5 pF. The

input source must be able to charge or discharge this capacitance

to its n-bit accuracy in one-half of a clock cycle. When the SHA

goes into track mode, the input source must charge or discharge

capacitor CH from the voltage already stored on CH to the new

voltage. In the worst case, a full-scale voltage step on the

input source must provide the charging current through the

RON (100

Ω) of Switch 1 and quickly (within 1/2 CLK period)

settle. This situation corresponds to driving a low input impedance.

On the other hand, when the source voltage equals the value

previously stored on CH, the hold capacitor requires no input

current and the equivalent input impedance is extremely high.

Adding series resistance between the output of the signal source

and the AIN pin reduces the drive requirements placed on the

signal source. Figure 20 shows this configuration.

AINP

AINN

< 50

SHUNT

< 50

Figure 20. Simple ADC Drive Configuration

The bandwidth of the particular application limits the size of this

resistor. To maintain the performance outlined in the data sheet

specifications, the resistor should be limited to 50

Ω or less. For

applications with signal bandwidths less than 10 MHz, the user

may proportionally increase the size of the series resistor. Alter-

natively, adding a shunt capacitance between the AIN pins can

RxI[7:4]

tHT

tTV

MCLK

Rx SYNC

Rx IQ

RxI[3:0]

RxQ[3:0]

RxQ[7:4]

RxI[7:4]'

RxI[3:0]'

RxQ[3:0]'

RxQ[7:4]'

RxI[3:0]"

RxI[7:4]"

IF-10

[11:2]

IF-12

[11:0]

IF-10

[11:2]'

IF-12

[11:0]'

IF-10

[11:2]"

IF-12

[11:0]"

IF-10

[11:2]'''

IF-12

[11:0]'''

IF-10

[11:2]""

IF-12

[11:0]""

Figure 18. Receive Timing Diagram

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