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AD9873JS 数据表(PDF) 9 Page - Analog Devices |
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AD9873JS 数据表(HTML) 9 Page - Analog Devices |
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9 / 39 page  REV. 0 AD9873 –9– PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Pin Function 1, 84, 87 AVDD Analog Supply Voltage 92, 95 10-/12-Bit ADC 2, 21, 70 DRGND Pin Driver Digital Ground 3, 22, 72 DRVDD Pin Driver Digital Supply Voltage 4–15 IF11–IF0 Multiplexed Output of IF10- and IF12-Bit ADCs 16–19 Rx IQ 3 Multiplexed Output of I and –Rx IQ 0 Q 8-Bit ADCs 20 Rx SYNC Demultiplexer Synchronization Output for IF and IQ ADCs 23 MCLK Master Clock Output Demultiplexer 24, 33, 38 DVDD Digital Supply Voltage 25, 34, DGND Digital Ground 39, 40 26 Tx SYNC Synchronization Input for Transmitter 27–32 Tx IQ 5 Multiplexed I and Q Input –Tx IQ 0 Data for Transmitter (Two’s Complement) 35, 36 PROFILE[1:0] Profile Selection Inputs 37 RESET Master Reset Input, Reset applies for all Interfaces and Registers 41 SCLK Serial Interface Input Clock 42 CS Serial Interface Chip Select 43 SDIO Serial Interface Data I/O 44 SDO Serial Interface Data Output 45 DGND Tx Digital Ground Tx Section 46 DVDD Tx Digital Supply Voltage Tx 47 PWR DOWN Transmit Power-Down Control Input 48 REFIO DAC Bandgap requires 0.1 µF Capacitor to Ground 49 FSADJ Full-Scale DAC Current Output Adjust with External Resistor 50 AGND Tx Analog Ground Tx Section 51 Tx– Transmitter DAC Output– 52 Tx+ Transmitter DAC Output+ 53 AVDD Tx Analog Supply Voltage Tx 54 DGND PLL PLL Digital Ground 55 DVDD PLL PLL Digital Supply Voltage 56 AVDD PLL PLL Analog Supply Voltage 57 PLL FILTER PLL Loop Filter Connection 58 AGND PLL PLL Analog Ground 59 DGND OSC Digital Ground Oscillator 60 XTAL Crystal Oscillator Inv. Output 61 OSC IN Oscillator Clock Input 62 DVDD OSC Digital Supply Oscillator 63 CA CLK Cable Amplifier Control Clock Output Pin No. Mnemonic Pin Function 64 CA DATA Cable Amplifier Control Data Output 65 CA ENABLE Cable Amplifier Control Enable Output 66 DVDD SD Supply Voltage Sigma Delta 67 SDELTA1 Sigma Delta Output Stream 1 68 SDELTA0 Sigma Delta Output Stream 0 69 DGND SD Ground Sigma Delta 71 REF CLK Programmable Reference Clock Output Derived from MCLK 73 AVDD IQ Analog Supply 8-Bit ADCs 74, 77, 80 AGND IQ Analog Ground 8-Bit ADCs 75 REFB8 Bottom Reference Decoupling IQ 8-Bit ADC’s Reference 76 REFT8 Top Reference Decoupling IQ 8-Bit ADC’s Reference 78 I IN– Inverting I Analog Input 79 I IN+ Noninverting I Analog Input 81 Q IN– Inverting Q Analog Input 82 Q IN+ Noninverting Q Analog Input 83, 88, 91, AGND Analog Ground 10-/12-Bit ADC 96, 99 85 REFB10 Bottom Reference Decoupling IF 10-Bit ADC’s Reference 86 REFT10 Top Reference Decoupling IF 10-Bit ADC’s Reference 89 IF10– Noninverting IF10 Analog Input 90 IF10+ Inverting IF10 Analog Input 93 REFB12 Bottom Reference Decoupling IF 12-Bit ADC’s Reference 94 REFT12 Top Reference Decoupling IF 12-Bit ADC’s Reference 97 IF12– Inverting IF12 Analog Input 98 IF12+ Noninverting IF12 Analog Input 100 VIDEO IN Single-Ended Video Input |
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