STM32F103CBT6 datasheet(75/102 Pages) STMICROELECTRONICS

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STM32F103x8, STM32F103xB

Electrical characteristics

Doc ID 13587 Rev 14

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5.3.18

12-bit ADC characteristics

Unless otherwise specified, the parameters given in Table 46 are derived from tests

performed under the ambient temperature, fPCLK2 frequency and VDDA supply voltage

conditions summarized in Table 9.

Note:

It is recommended to perform a calibration after each power-up.

Table 46.

ADC characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VDDA

Power supply

2.4

3.6

VREF+

Positive reference voltage

2.4

VDDA

IVREF

Current on the VREF input pin

160(1)

220(1)

µA

fADC

ADC clock frequency

0.6

MHz

(2)

Sampling rate

0.05

MHz

fTRIG

(2)

External trigger frequency

fADC = 14 MHz

823

kHz

1/fADC

VAIN

(3)

Conversion voltage range

0 (VSSA or VREF-

tied to ground)

VREF+

RAIN

(2)

External input impedance

See Equation 1 and

Table 47 for details

RADC

(2)

Sampling switch resistance

CADC

(2)

Internal sample and hold

capacitor

8pF

tCAL

(2)

Calibration time

fADC = 14 MHz

5.9

µs

1/fADC

tlat

(2)

Injection trigger conversion

latency

fADC = 14 MHz

0.214

µs

3(4)

1/fADC

tlatr

(2)

Regular trigger conversion

latency

fADC = 14 MHz

0.143

µs

2(4)

1/fADC

(2)

Sampling time

fADC = 14 MHz

0.107

17.1

µs

1.5

239.5

1/fADC

tSTAB

(2)

Power-up time

µs

tCONV

(2)

Total conversion time

(including sampling time)

fADC = 14 MHz

µs

14 to 252 (tS for sampling +12.5 for

successive approximation)

1/fADC

Based on characterization, not tested in production.

Guaranteed by design, not tested in production.

In devices delivered in VFQFPN and LQFP packages, VREF+ is internally connected to VDDA and VREF- is internally

connected to VSSA. Devices that come in the TFBGA64 package have a VREF+ pin but no VREF- pin (VREF- is internally

connected to VSSA), see Table 5 and Figure 7.

For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 46.

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