STM32F103CBT6 datasheet(15/102 Pages) STMICROELECTRONICS

15 / 102 page

STM32F103x8, STM32F103xB

Description

Doc ID 13587 Rev 14

15/102

This hardware block provides flexible interrupt management features with minimal interrupt

latency.

2.3.6

External interrupt/event controller (EXTI)

The external interrupt/event controller consists of 19 edge detector lines used to generate

interrupt/event requests. Each line can be independently configured to select the trigger

event (rising edge, falling edge, both) and can be masked independently. A pending register

maintains the status of the interrupt requests. The EXTI can detect an external line with a

pulse width shorter than the Internal APB2 clock period. Up to 80 GPIOs can be connected

to the 16 external interrupt lines.

2.3.7

Clocks and startup

System clock selection is performed on startup, however the internal RC 8 MHz oscillator is

selected as default CPU clock on reset. An external 4-16 MHz clock can be selected, in

which case it is monitored for failure. If failure is detected, the system automatically switches

back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full

interrupt management of the PLL clock entry is available when necessary (for example on

failure of an indirectly used external crystal, resonator or oscillator).

Several prescalers allow the configuration of the AHB frequency, the high-speed APB

(APB2) and the low-speed APB (APB1) domains. The maximum frequency of the AHB and

the high-speed APB domains is 72 MHz. The maximum allowed frequency of the low-speed

APB domain is 36 MHz. See Figure 2 for details on the clock tree.

2.3.8

Boot modes

At startup, boot pins are used to select one of three boot options:

●

Boot from User Flash

●

Boot from System Memory

●

Boot from embedded SRAM

The boot loader is located in System Memory. It is used to reprogram the Flash memory by

using USART1. For further details please refer to AN2606.

2.3.9

Power supply schemes

●

VDD = 2.0 to 3.6 V: external power supply for I/Os and the internal regulator.

Provided externally through VDD pins.

●

VSSA, VDDA = 2.0 to 3.6 V: external analog power supplies for ADC, reset blocks, RCs

and PLL (minimum voltage to be applied to VDDA is 2.4 V when the ADC is used).

VDDA and VSSA must be connected to VDD and VSS, respectively.

●

VBAT = 1.8 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup

registers (through power switch) when VDD is not present.

For more details on how to connect power pins, refer to Figure 14: Power supply scheme.

2.3.10

Power supply supervisor

The device has an integrated power-on reset (POR)/power-down reset (PDR) circuitry. It is

always active, and ensures proper operation starting from/down to 2 V. The device remains

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