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ADP2380AREZ-R7 数据表(PDF) 21 Page - Analog Devices

部件名 ADP2380AREZ-R7
功能描述  20 V, 4 A Synchronous Step-Down Regulator with Low-Side Driver
PDF  28 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADP2380AREZ-R7 数据表(HTML) 21 Page - Analog Devices

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Data Sheet
ADP2380
Rev. 0 | Page 21 of 28
LOW-SIDE MOSFET SELECTION
A low RDSON N-channel MOSFET is chosen as a high efficiency
solution. The breakdown voltage of the MOSFET must be
higher than 1.2 × VIN, and the drain current must be larger than
1.2 × ILIMIT.
It is recommended to use a 30 V, N-channel MOSFET, such as
the FDS6298 from Fairchild. The RDSON of the FDS6298 at a 4.5 V
driver voltage is 9.4 mΩ, and the total gate charge at 5 V is 10 nC.
COMPENSATION COMPONENTS
For better load transient and stability performance, set the cross
frequency, fC, at fSW/10. In this case, fC = 1/500 kHz = 50 kHz.
)
)(
(
)
)(
(
_
_
_
0
_
A
r
C
R
B
C
C
R
r
C
C
C
R
B
R
A
r
C
R
B
C
C
R
r
g
B
C
0
C
C
CP
C
C
0
EA
CP
EA
C
C
C
EA
C
0
C
C
CP
C
C
m
EA
C
+
+
=
+
=
+
+
−
×
=
where:
RC =
VI
m
REF
C
OUT
OUT
A
g
V
f
C
V
×
×
×
×
×
×
π
2
=
A/V
7
.
8
μS
470
V
6
.
0
kHz
50
μF
32
2
V
3
.
3
2
×
×
×
×
×
×
×
π
= 27.1 kΩ
CC =
(
)
C
OUT
ESR
R
C
R
R
×
+
=
k
Ω
1
.
27
μF
32
2
)
002
.
0
A
4
V/
3
.
3
(
×
×
Ω
+
= 1.96 nF
CCP =
k
Ω
1
.
27
μF
32
2
002
.
0
×
×
Ω
=
×
C
OUT
ESR
R
C
R
= 4.73 pF
A =
(
)
k
Ω
21
.
2
k
Ω
10
k
Ω
21
.
2
k
Ω
10
1
+
×
=
×
+
+
0
m
BOT
TOP
BOT
TOP
r
g
R
R
R
R
×
(1 + 470 µS × 40 MΩ) = 3.4 × 107
B =
M
Ω
40
10
4
.
3
(
μS
470
1
nF)
96
.
1
pF
73
.
4
(
M
Ω
40
)
(
1
)
(
7
+
×
×
+
+
×
=
+
+
+
0
m
C
CP
0
r
A
g
C
C
r
=
2.26 × 10−6
This results in the following:
RC_EA = 52.3 kΩ.
CC_EA = 1055 pF.
CCP_EA = 2.45 pF.
Choose the standard values for RC_EA = 49.9 kΩ, CC_EA = 1000 pF,
and CCP_EA = 2.2 pF.
Figure 35 shows the Bode plot at 4 A. The cross frequency is
43 kHz, and the phase margin is 59°.
60
48
36
24
12
0
–60
–48
–36
–24
–12
180
144
108
72
36
0
–180
–144
–108
–72
–36
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 35. Bode Plot at 4 A
SOFT START TIME PROGRAM
The soft start feature allows the output voltage to ramp up in a
controlled manner, eliminating output voltage overshoot during
soft start and limiting the inrush current. Set the soft start time
to 4 ms.
CSS =
V
6
.
0
μA
2
.
3
ms
4
V
6
.
0
_
_
×
=
×
UP
SS
EXT
SS
I
t
= 21.3 nF
Choose a standard component value, CSS = 22 nF.
INPUT CAPACITOR SELECTION
A minimum 10 μF ceramic capacitor must be placed near the
PVIN pin. In this application, one 10 μF, X5R, 25 V ceramic
capacitor is recommended.
ADP2380
1
PVIN
PVIN
UVLO
PGOOD
RT
SYNC
EN/SS
COMP
BST
SW
SW
LD
VREG
PGND
GND
FB
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
RTOP
10kΩ
1%
RBOT
2.21kΩ
1%
CSS
22nF
ROSC
100kΩ
CIN
10µF
25V
COUT1
47µF
6.3V
COUT2
47µF
6.3V
VOUT = 3.3V
CBST
0.1µF
CVREG
1µF
L1
4.7µH
VIN = 12V
CC_EA
1000pF
CCP_EA
2.2pF
RC_EA
49.9kΩ
M1
FDS6298
Figure 36. Design Example Schematic



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