ADP2380AREZ-R7 datasheet(24/28 Pages) AD

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ADP2380

Data Sheet

Rev. 0 | Page 24 of 28

CIRCUIT BOARD LAYOUT RECOMMENDATIONS

Good circuit board layout is essential for obtaining the best

performance from the ADP2380. Poor printed circuit board

(PCB) layout degrades the output regulation as well as the

electromagnetic interface (EMI) and electromagnetic

compatibility (EMC) performance. Figure 38 shows a PCB

layout example. For optimum layout, use the following guidelines:

•

Use separate analog ground and power ground planes.

Connect the ground reference of sensitive analog circuitry,

such as output voltage divider components, to analog

ground. In addition, connect the ground reference of

power components, such as input and output capacitors

and a low-side MOSFET, to power ground. Connect both

ground planes to the exposed pad of the ADP2380.

•

Place the input capacitor, inductor, low-side MOSFET, and

output capacitor as close to the IC as possible, and use

short traces.

•

Ensure that the high current loop traces are as short and

as wide as possible. Make the high current path from the

input capacitor through the inductor, the output capacitor,

and the power ground plane back to the input capacitor as

short as possible. To accomplish this, ensure that the input

and output capacitors share a common power ground plane.

In addition, ensure that the high current path from the

power ground plane through the external MOSFET,

inductor, and output capacitor back to the power ground

plane is as short as possible by tying the MOSFET source

node to the PGND plane as close as possible to the input

and output capacitors.

•

Make the low-side driver path from the LD pin of the

ADP2380 to the external MOSFET gate node and back to

the PGND pin of the ADP2380 as short as possible, and

use a wide trace for better noise immunity.

•

Connect the exposed pad of the ADP2380 to a large copper

plane to maximize its power dissipation capability for

better thermal dissipation.

•

Place the feedback resistor divider network as close as

possible to the FB pin to prevent noise pickup. Try to

minimize the length of the trace that connects the top of

the feedback resistor divider to the output while keeping

the trace away from the high current traces and the

switching node to avoid noise pickup. To further reduce

noise pickup, place an analog ground plane on either side

of the FB trace and ensure that the trace is as short as

possible to reduce parasitic capacitance pickup.

ADP2380

PVIN

UVLO

PGOOD

SYNC

EN/SS

COMP

BST

VREG

PGND

GND

ROSC

RTOP

RBOT

CSS

CIN

COUT

VOUT

CBST

CVREG

VIN

CC_EA

CCP_EA

RC_EA

FET

Figure 37. High Current Path in the PCB Circuit

ADP2380AREZ-R7 数据表(PDF) 24 Page - Analog Devices

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