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ADP2380AREZ-R7 数据表(PDF) 26 Page - Analog Devices

部件名 ADP2380AREZ-R7
功能描述  20 V, 4 A Synchronous Step-Down Regulator with Low-Side Driver
PDF  28 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADP2380AREZ-R7 数据表(HTML) 26 Page - Analog Devices

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ADP2380
Data Sheet
Rev. 0 | Page 26 of 28
TYPICAL APPLICATIONS CIRCUITS
ADP2380
1
PVIN
PVIN
UVLO
PGOOD
RT
SYNC
EN/SS
COMP
BST
SW
SW
LD
VREG
PGND
GND
FB
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
RTOP
10kΩ
1%
RBOT
10kΩ
1%
CSS
22nF
CIN
10µF
25V
COUT
470µF
6.3V
VOUT = 1.2V
CBST
0.1µF
CVREG
1µF
L1
2.2µH
VIN = 12V
CCP
68pF
CC
2.2nF
RC
68kΩ
M1
FDS6298
ROSC
100kΩ
Figure 39. Compensation Network Between COMP and GND, VIN = 12 V, VOUT = 1.2 V, IOUT = 4 A, fSW = 500 kHz
ADP2380
1
PVIN
PVIN
UVLO
PGOOD
RT
SYNC
EN/SS
COMP
BST
SW
SW
LD
VREG
PGND
GND
FB
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
RTOP
20kΩ
1%
RBOT
10kΩ
1%
CSS
22nF
CIN
10µF
25V
COUT1
100µF
6.3V
COUT2
100µF
6.3V
VOUT = 1.8V
CBST
0.1µF
CVREG
1µF
L1
2.2µH
VIN = 12V
CC_EA
470pF
CCP_EA
2.2pF
RC_EA
110kΩ
M1
FDS6298
R1
7.32kΩ
1%
R2
1kΩ
1%
ROSC
100kΩ
Figure 40. Programming Input Voltage UVLO Rising Threshold at 10 V, VIN = 12 V, VOUT = 1.8 V, IOUT = 4 A, fSW = 500 kHz
ADP2380
1
PVIN
PVIN
UVLO
PGOOD
RT
SYNC
EN/SS
COMP
BST
SW
SW
LD
VREG
PGND
GND
FB
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
ROSC
82kΩ
RTOP
22kΩ
1%
RSOT
3kΩ
1%
CIN
10µF
25V
COUT
100µF
6.3V
VOUT = 5V
CBST
0.1µF
CVREG
1µF
L1
4.7µH
VIN = 12V
CC_EA
820pF
CCP_EA
1pF
RC_EA
100kΩ
M1
FDS6298
Figure 41. Using Internal Soft Start, Programming Switching Frequency at 600 kHz, VIN = 12 V, VOUT = 5 V, IOUT = 4 A, fSW = 600 kHz



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