T0146-09

WCLK

BCLK

DIN

t (WS)

d

t (WS)

d

t (DI)

S

t (DI)

h

t

f

t

r

TAS2521

www.ti.com

SLAS687A – FEBRUARY 2013 – REVISED FEBRUARY 2013

3.5.3

DSP Timing in Master Mode

All specifications at 25°C, DVDD = 1.8 V

Note: All timing specifications are measured at characterization but not tested at final test.

IOVDD = 1.8 V

IOVDD = 3.3 V

PARAMETER

UNIT

MIN

MAX

MIN

MAX

WCLK delay

45

45

ns

DIN setup

8

6

ns

DIN hold

8

6

ns

Rise time

25

10

ns

Fall time

25

10

ns

Figure 3-3. DSP Timing in Master Mode

Copyright © 2013, Texas Instruments Incorporated

ELECTRICAL SPECIFICATIONS

11

Submit Documentation Feedback

Product Folder Links: TAS2521