STO

STA

STA

STO

SDA

SCL

t

BUF

t

LOW

t

SU;STA

t

HIGH

t

HD;STA

t

r

t

HD;STA

t

HD;DAT

t

SU;DAT

t

SU;STO

t

f

T0295-02

TAS2521

www.ti.com

SLAS687A – FEBRUARY 2013 – REVISED FEBRUARY 2013

3.5.5

I

All specifications at 25°C, DVDD = 1.8 V

Note: All timing specifications are measured at characterization but not tested at final test.

PARAMETER

Standard-Mode

Fast-Mode

UNITS

MIN

TYP

MAX

MIN

TYP

MAX

SCL clock frequency

0

100

0

400

kHz

Hold time (repeated) START condition.

After this period, the first clock pulse is

4

0.8

μs

generated.

LOW period of the SCL clock

4.7

1.3

μs

HIGH period of the SCL clock

4

0.6

μs

Setup time for a repeated START

4.7

0.8

μs

condition

0

3.45

0

0.9

μs

Data setup time

250

100

ns

SDA and SCL rise time

1000

300

ns

SDA and SCL fall time

300

300

ns

Set-up time for STOP condition

4

0.8

μs

Bus free time between a STOP and

4.7

1.3

μs

START condition

Capacitive load for each bus line

400

400

pF

Copyright © 2013, Texas Instruments Incorporated

ELECTRICAL SPECIFICATIONS

13

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