TAS2521

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SLAS687A – FEBRUARY 2013 – REVISED FEBRUARY 2013

Table 5-3. AVDD LDO Settings

Page-1, Register 2, D(5:4)

LDO Output

00

1.8 V

01

1.6 V

10

1.7 V

00

1.5 V

For more detailed information see the TAS2521 Application Reference Guide (SLAU456).

5.6.5

POR

TAS2521 has a POR (Power On Reset) function. This function insures that all registers are automatically

set to defaults when a proper power up sequence is executed.

For more detailed information see the TAS2521 Application Reference Guide (SLAU456).

5.6.6

CLOCK Generation and PLL

The TAS2521 supports a wide range of options for generating clocks for the DAC sections as well as

interface and other control blocks. The clocks for the DAC require a source reference clock. This clock can

be provided on a variety of device pins, such as the MCLK, BCLK, or GPIO pins. The source reference

clock for the codec can be chosen by programming the CODEC_CLKIN value on page 0, register 4, bits

D1–D0. The CODEC_CLKIN can then be routed through highly-flexible clock dividers shown in to

generate the various clocks required for the DAC and the miniDSP section. In the event that the desired

audio clocks cannot be generated from the reference clocks on MCLK, BCLK, or GPIO, the TAS2521 also

provides the option of using the on-chip PLL which supports a wide range of fractional multiplication

values to generate the required clocks. Starting from CODEC_CLKIN, the TAS2521 provides several

programmable clock dividers to help achieve a variety of sampling rates for the DAC and clocks for the

miniDSP sections.

For more detailed information see the TAS2521 Application Reference Guide (SLAU456).

5.6.7

Digital Audio and Control Interface

5.6.7.1

Digital Audio Interface

Audio data is transferred between the host processor and the TAS2521 via the digital audio data serial

interface, or audio bus. The audio bus on this device is flexible, including left- or right-justified data

multichannel operation, flexible master/slave configurability for each bus clock line, and the ability to

communicate with multiple devices within a system directly.

operation, where communication with standard telephony PCM interfaces is supported within the TDM

mode. These modes are all MSB-first, with data width programmable as 16, 20, 24, or 32 bits by

configuring page 0, register 27, bits D5–D4. In addition, the word clock and bit clock can be independently

configured in either master or slave mode for flexible connectivity to a wide variety of processors. The

word clock is used to define the beginning of a frame, and may be programmed as either a pulse or a

square-wave signal. The frequency of this clock corresponds to the maximum of the selected DAC

sampling frequencies.

For more detailed information see the TAS2521 Application Reference Guide (SLAU456).

5.6.7.2

Control Interface

The TAS2521 control interface supports SPI or I2C communication protocols, with the protocol selectable

using the SPI_SEL pin. For SPI, SPI_SEL should be tied high; for I2C, SPI_SEL should be tied low. It is

not recommended to change the state of SPI_SEL during device operation.

Copyright © 2013, Texas Instruments Incorporated

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