ADE7753

Rev. C | Page 55 of 60

ADE7753 REGISTER DESCRIPTIONS

All ADE7753 functionality is accessed via the on-chip registers. Each register is accessed by first writing to the communications register

and then transferring the register data. A full description of the serial interface protocol is given in the ADE7753 Serial Interface section.

COMMUNICATIONS REGISTER

The communications register is an 8-bit, write-only register which controls the serial data transfer between the ADE7753 and the host

processor. All data transfer operations must begin with a write to the communications register. The data written to the communications

register determines whether the next operation is a read or a write and which register is being accessed. Table 13 outlines the bit

designations for the communications register.

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

W/R

0

A5

A4

A3

A2

A1

A0

Table 13. Communications Register

Bit Location

Bit Mnemonic

Description

0 to 5

A0 to A5

The six LSBs of the communications register specify the register for the data transfer operation.

Table 12 lists the address of each ADE7753 on-chip register.

6

RESERVED

This bit is unused and should be set to 0.

7

W/R

When this bit is a Logic 1, the data transfer operation immediately following the write to the

communications register is interpreted as a write to the ADE7753.

When this bit is a Logic 0, the data transfer operation immediately following the write to the

communications register is interpreted as a read operation.

MODE REGISTER (0x09)

The ADE7753 functionality is configured by writing to the mode register. Table 14 describes the functionality of each bit in the register.

Table 14. Mode Register

Bit Location

Bit Mnemonic

Default

Value

Description

0

DISHPF

0

HPF (high-pass filter) in Channel 1 is disabled when this bit is set.

1

DISLPF2

0

LPF (low-pass filter) after the multiplier (LPF2) is disabled when this bit is set.

2

DISCF

1

Frequency output CF is disabled when this bit is set.

3

DISSAG

1

Line voltage sag detection is disabled when this bit is set.

4

ASUSPEND

0

By setting this bit to Logic 1, both ADE7753 A/D converters can be turned off.

In normal operation, this bit should be left at Logic 0. All digital functionality can be

stopped by suspending the clock signal at CLKIN pin.

5

TEMPSEL

0

Temperature conversion starts when this bit is set to 1. This bit is automatically reset to 0

when the temperature conversion is finished.

6

SWRST

0

Software Chip Reset. A data transfer should not take place to the ADE7753 for at least

18 μs after a software reset.

7

CYCMODE

0

Setting this bit to Logic 1 places the chip into line cycle energy accumulation mode.

8

DISCH1

0

ADC 1 (Channel 1) inputs are internally shorted together.

9

DISCH2

0

ADC 2 (Channel 2) inputs are internally shorted together.

10

SWAP

0

By setting this bit to Logic 1 the analog inputs V2P and V2N are connected to ADC 1 and

the analog inputs V1P and V1N are connected to ADC 2.

12, 11

DTRT1, 0

00

These bits are used to select the waveform register update rate.

DTRT 1

DTRT0

Update Rate

0

0

27.9 kSPS (CLKIN/128)

0

1

14 kSPS (CLKIN/256)

1

0

7 kSPS (CLKIN/512)

1

1

3.5 kSPS (CLKIN/1024)