ADE7753ARS datasheet(19/60 Pages) AD

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ADE7753

Rev. C | Page 19 of 60

The flag in the interrupt status register as well as the IRQ output

are reset to their default values when the interrupt status register

with reset (RSTSTATUS) is read.

Zero-Crossing Timeout

The zero-crossing detection also has an associated timeout

(1 LSB) every 128/CLKIN seconds. The register is reset to its

user programmed full-scale value every time a zero crossing is

detected on Channel 2. The default power on value in this

a zero crossing is detected and the DISSAG bit in the mode

of a zero crossing is also indicated on the IRQ pin if the ZXTO

enable bit in the interrupt enable register is set to Logic 1.

Irrespective of the enable bit setting, the ZXTO flag in the

interrupt status register is always set when the internal ZXTOUT

section.

ADE7753 Interrupts

The ZXOUT register can be written/read by the user and has an

address of 1Dh—see the ADE7753 Serial Interface section. The

resolution of the register is 128/CLKIN seconds per LSB. Thus the

maximum delay for an interrupt is 0.15 second (128/CLKIN × 212).

Figure 41 shows the mechanism of the zero-crossing timeout

detection when the line voltage stays at a fixed dc level for more

than CLKIN/128 × ZXTOUT seconds.

12-BIT INTERNAL

ZXTOUT

CHANNEL 2

ZXTO

DETECTION

BIT

02875-0-041

Figure 41. Zero-Crossing Timeout Detection

PERIOD MEASUREMENT

The ADE7753 also provides the period measurement of the

line. The period register is an unsigned 16-bit register and is

updated every period. The MSB of this register is always zero.

The resolution of this register is 2.2 μs/LSB when CLKIN =

3.579545 MHz, which represents 0.013% when the line fre-

quency is 60 Hz. When the line frequency is 60 Hz, the value of

the period register is approximately CLKIN/4/32/60 Hz × 16 =

7457d. The length of the register enables the measurement of line

frequencies as low as 13.9 Hz.

The period register is stable at ±1 LSB when the line is

established and the measurement does not change. A settling

time of 1.8 seconds is associated with this filter before the

measurement is stable.

POWER SUPPLY MONITOR

The ADE7753 also contains an on-chip power supply monitor.

The analog supply (AVDD) is continuously monitored by the

ADE7753. If the supply is less than 4 V ± 5%, then the

ADE7753 goes into an inactive state, that is, no energy is

accumulated when the supply voltage is below 4 V. This is

useful to ensure correct device operation at power-up and

during power-down. The power supply monitor has built-in

hysteresis and filtering, which give a high degree of immunity

to false triggering due to noisy supplies.

AVDD

ADE7753

POWER-ON

INACTIVE

STATE

SAG

INACTIVE

ACTIVE

INACTIVE

TIME

02875-0-042

Figure 42. On-Chip Power Supply Monitor

As seen in Figure 42, the trigger level is nominally set at 4 V.

The tolerance on this trigger level is about ±5%. The SAG pin

can also be used as a power supply monitor input to the MCU.

The SAG pin goes logic low when the ADE7753 is in its inactive

state. The power supply and decoupling for the part should be

such that the ripple at AVDD does not exceed 5 V ±5%, as

specified for normal operation.

LINE VOLTAGE SAG DETECTION

In addition to the detection of the loss of the line voltage signal

(zero crossing), the ADE7753 can also be programmed to detect

when the absolute value of the line voltage drops below a

certain peak value for a number of line cycles. This condition is

illustrated in Figure 43.

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