ADE7753ARSZ datasheet(49/60 Pages) AD

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ADE7753

Rev. C | Page 49 of 60

ADE7753 SERIAL INTERFACE

All ADE7753 functionality is accessible via several on-chip

registers—see Figure 89. The contents of these registers can be

updated or read using the on-chip serial interface. After power-

on or toggling the RESET pin low or a falling edge on CS, the

ADE7753 is placed in communications mode. In communica-

tions mode, the ADE7753 expects a write to its communications

determines whether the next data transfer operation is a read

or a write and also which register is accessed. Therefore all data

transfer operations with the ADE7753, whether a read or a write,

must begin with a write to the communications register.

COMMUNICATIONS

OUT

ADDRESS

DECODE

DIN

DOUT

02875-0-078

Figure 89. Addressing ADE7753 Registers via the Communications Register

The communications register is an 8-bit wide register. The MSB

determines whether the next data transfer operation is a read or

a write. The six LSBs contain the address of the register to be

accessed—see the Communications Register section for a more

detailed description.

Figure 90 and Figure 91 show the data transfer sequences for a

read and write operation, respectively. On completion of a data

transfer (read or write), the ADE7753 once again enters

communications mode. A data transfer is complete when the

LSB of the ADE7753 register being addressed (for a write or a

read) is transferred to or from the ADE7753.

MULTIBYTE

COMMUNICATIONS REGISTER WRITE

DIN

SCLK

DOUT

READ DATA

ADDRESS

02875-0-079

Figure 90. Reading Data from the ADE7753 via the Serial Interface

COMMUNICATIONS REGISTER WRITE

DIN

SCLK

ADDRESS

02875-0-080

MULTIBYTE

READ DATA

Figure 91. Writing Data to the ADE7753 via the Serial Interface

The serial interface of the ADE7753 is made up of four signals:

SCLK, DIN, DOUT, and CS. The serial clock for a data transfer

is applied at the SCLK logic input. This logic input has a

Schmitt-trigger input structure that allows slow rising (and

falling) clock edges to be used. All data transfer operations are

synchronized to the serial clock. Data is shifted into the

ADE7753 at the DIN logic input on the falling edge of SCLK.

Data is shifted out of the ADE7753 at the DOUT logic output

on a rising edge of SCLK. The CS logic input is the chip-select

input. This input is used when multiple devices share the serial

bus. A falling edge on CS also resets the serial interface and

places the ADE7753 into communications mode. The CS input

should be driven low for the entire data transfer operation.

Bringing CS high during a data transfer operation aborts the

transfer and places the serial bus in a high impedance state. The

CS logic input can be tied low if the ADE7753 is the only device

on the serial bus. However, with CS tied low, all initiated data

transfer operations must be fully completed, i.e., the LSB of each

bringing the ADE7753 back into communications mode

without resetting the entire device by using RESET.

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