ADE7753ARSZ datasheet(8/60 Pages) AD

8 / 60 page

ADE7753

Rev. C | Page 8 of 60

TERMINOLOGY

Measurement Error

The error associated with the energy measurement made by the

ADE7753 is defined by the following formula:

100

7753

⎟

⎠

⎞

⎜

⎝

⎛

−

Energy

True

Energy

True

ADE

Energy

Error

Percentage

Phase Error between Channels

The digital integrator and the high-pass filter (HPF) in Channel 1

have a non-ideal phase response. To offset this phase response

and equalize the phase response between channels, two phase-

correction networks are placed in Channel 1: one for the digital

integrator and the other for the HPF. The phase correction

networks correct the phase response of the corresponding

component and ensure a phase match between Channel 1

(current) and Channel 2 (voltage) to within ±0.1° over a range

of 45 Hz to 65 Hz with the digital integrator off. With the digital

integrator on, the phase is corrected to within ±0.4°

over a range of 45 Hz to 65 Hz.

Power Supply Rejection

This quantifies the ADE7753 measurement error as a percentage

of reading when the power supplies are varied. For the ac PSR

measurement, a reading at nominal supplies (5 V) is taken. A

second reading is obtained with the same input signal levels

when an ac (175 mV rms/120 Hz) signal is introduced onto the

supplies. Any error introduced by this ac signal is expressed as a

percentage of reading—see the Measurement Error definition.

For the dc PSR measurement, a reading at nominal supplies

(5 V) is taken. A second reading is obtained with the same input

signal levels when the supplies are varied ±5%. Any error

introduced is again expressed as a percentage of the reading.

ADC Offset Error

The dc offset associated with the analog inputs to the ADCs. It

means that with the analog inputs connected to AGND, the

ADCs still see a dc analog input signal. The magnitude of the

offset depends on the gain and input range selection—see the

Typical Performance Characteristics section. However, when

HPF1 is switched on, the offset is removed from Channel 1

(current) and the power calculation is not affected by this offset.

The offsets can be removed by performing an offset

calibration—see the Analog Inputs section.

Gain Error

The difference between the measured ADC output code (minus

the offset) and the ideal output code—see the Channel 1 ADC

and Channel 2 ADC sections. It is measured for each of the

input ranges on Channel 1 (0.5 V, 0.25 V, and 0.125 V). The

difference is expressed as a percentage of the ideal code.

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