AR1010T-ISLASHML datasheet(19/70 Pages) MICROCHIP

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Preliminary

DS41393B-page 19

AR1000 SERIES RESISTIVE TOUCH SCREEN CONTROLLER

Master receives eight data bits (MSb first)

presented on SDA by the AR1021, at eight

sequential master clock (SCL) cycles. The data

is latched out on SCL falling edges to ensure it

is valid during the subsequent SCL high time.

If data transfer is not complete, then:

- Master acknowledges (ACK) reception of the

eight data bits by presenting a low on SDA,

followed by a low-high-low on SCL.

- Go to step 5.

If data transfer is complete, then:

- Master acknowledges (ACK) reception of the

eight data bits and a completed data transfer

by presenting a high on SDA, followed by a

low-high-low on SCL.

Master presents a “Stop” bit to the AR1021 by

taking SCL low-high, followed by taking SDA

low-to-high.

4.5

Master Write Bit Timing

Master write is to send supported commands to the

AR1021.

• Address bits are latched into the AR1021 on the

rising edges of SCL.

• Data bits are latched into the AR1021 on the

rising edges of SCL.

• ACK is presented by AR1021 on the ninth clock.

• The master must monitor the SCL pin prior to

asserting another clock pulse, as the AR1021

may be holding off the master by stretching the

clock.

FIGURE 4-2:

I2C MASTER WRITE BIT TIMING DIAGRAM

Steps

SCL and SDA lines are Idle high.

Master presents “Start” bit to the AR1021 by

taking SDA high-to-low, followed by taking SCL

high-to-low.

Master presents 7-bit Address, followed by a

R/W = 0 (Write mode) bit to the AR1021 on

SDA, at the rising edge of eight master clock

(SCL) cycles.

AR1021 compares the received address to its

device ID. If they match, the AR1021

acknowledges (ACK) the master sent address

by presenting a low on SDA, followed by a

low-high-low on SCL.

Master monitors SCL, as the AR1021 may be

“clock stretching”, holding SCL low to indicate

the master should wait.

Master presents eight data bits (MSb first) to the

AR1021 on SDA, at the rising edge of eight mas-

ter clock (SCL) cycles.

AR1021 acknowledges (ACK) receipt of the

eight data bits by presenting a low on SDA, fol-

lowed by a low-high-low on SCL.

If data transfer is not complete, then go to step 5.

Master presents a “Stop” bit to the AR1021 by

taking SCL low-high, followed by taking SDA

low-to-high.

4.6

Clock Stretching

The master normally controls the clock line SCL. Clock

stretching is when the slave device holds the SCL line

low, indicating to the master that it is not ready to

continue the communications.

During communications, the AR1021 may hold off the

master by stretching the clock with a low on SCL.

The master must monitor the slave SCL pin to ensure

the AR1021 is not holding it low, prior to asserting

another clock pulse for transmitting or receiving.

4.7

AR1020 Write Conditions

The AR1020 part does not implement clock stretching

on write conditions.

A 50 us delay is needed before the Stop bit, when

clocking a command to the AR1020.

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