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ADRF6806ACPZ-R7 数据表(PDF) 16 Page - Analog Devices

部件名 ADRF6806ACPZ-R7
功能描述  50 MHz to 525 MHz Quadrature Demodulator with Fractional-N PLL and VCO
PDF  36 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADRF6806ACPZ-R7 数据表(HTML) 16 Page - Analog Devices

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ADRF6806
Data Sheet
Rev. B | Page 16 of 36
Register 1—Modulus Divide Control
With R1[2:0] set to 001, the on-chip modulus divide control register is programmed as shown in Figure 34. The MOD value is the preset
fractional modulus ranging from 1 to 2047.
MODULUS DIVIDE RATIO
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15
DB14
DB13
DB12 DB11 DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
0
0
0
0
0
MD10
MD9
MD8
MD7
MD6
MD5
MD4
MD3
MD2
MD1
MD0
C3(0)
C2(0) C1(1)
MD10
MD9
MD8
MD7
MD6
MD5
MD4
MD3
MD2
MD1
MD0
0
0
000000001
0
0000000010
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
1
1000000000
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
1
111111
1111
MODULUS VALUE
...
...
2047
CONTROL BITS
1
1536 (DEFAULT)
2
...
...
Figure 34. Modulus Divide Control Register (R1)
Register 2—Fractional Divide Control
With R2[2:0] set to 010, the on-chip fractional divide control register is programmed as shown in Figure 35. The FRAC value is the preset
fractional modulus ranging from 0 to MOD − 1.
FD10
FD9
FD8FD7FD6FD5FD4FD3FD2FD1FD0
0
00
000
000
00
0
00
000
000
01
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
0
11
000
000
00
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
FRACTIONAL VALUE MUST BE LESS THAN MODULUS
FRACTIONAL VALUE
0
1
...
...
768 (DEFAULT)
...
...
<MDR
FRACTIONAL DIVIDE RATIO
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16
DB15
DB14 DB13
DB12 DB11 DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
CONTROL BITS
00
0000
000
0
FD10
FD9
FD8
FD7
FD6
FD5
FD4
FD3
FD2
FD1
FD0
C3(0)
C2(1)
C1(0)
Figure 35. Fractional Divide Control Register (R2)
Register 3—Σ-Δ Modulator Dither Control
With R3[2:0] set to 011, the on-chip Σ-Δ modulator dither control register is programmed as shown in Figure 36. The dither restart value
can be programmed from 0 to 217 to 1, though a value of 1 is typically recommended.
DITHER
ENABLE
DB23
DB22
DB21
DB20
DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
DITH1
DITH0
DEN
DV16 DV15 DV14 DV13 DV12 DV11 DV10 DV9 DV8 DV7 DV6 DV5 DV4 DV3 DV2 DV1 DV0 C3(0) C2(1) C1(1)
DITH1
DITH0
00
01
10
11
DEN
0
1
DITHER
MAGNITUDE
DITHER RESTART VALUE
CONTROL BITS
DITHER MAGNITUDE
15 (DEFAULT)
7
3
1 (RECOMMENDED)
DITHER ENABLE
DISABLE
ENABLE (DEFAULT, RECOMMENDED)
DV16 DV15 DV14 DV13 DV12 DV11 DV10 DV9 DV8 DV7 DV6 DV5 DV4 DV3 DV2 DV1 DV0
00
000
00
000
00
000
01
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
11
111
11
111
11
111
11
0x00001 (DEFAULT)
...
...
0x1FFFF
DITHER RESTART
VALUE
Figure 36. Σ-Δ Modulator Dither Control Register (R3)



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