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ADRF6806ACPZ-R7 数据表(PDF) 2 Page - Analog Devices

部件名 ADRF6806ACPZ-R7
功能描述  50 MHz to 525 MHz Quadrature Demodulator with Fractional-N PLL and VCO
PDF  36 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADRF6806ACPZ-R7 数据表(HTML) 2 Page - Analog Devices

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ADRF6806
Data Sheet
Rev. B | Page 2 of 36
TABLE OF CONTENTS
Features .............................................................................................. 1
 
Applications....................................................................................... 1
 
General Description ......................................................................... 1
 
Functional Block Diagram .............................................................. 1
 
Revision History ............................................................................... 2
 
Specifications..................................................................................... 3
 
Timing Characteristics ................................................................ 5
 
Absolute Maximum Ratings............................................................ 6
 
ESD Caution.................................................................................. 6
 
Pin Configuration and Function Descriptions............................. 7
 
Typical Performance Characteristics ............................................. 9
 
Synthesizer/PLL .......................................................................... 12
 
Complementary Cumulative Distribution Functions (CCDF)
....................................................................................................... 13
 
Circuit Description......................................................................... 14
 
LO Quadrature Drive................................................................. 14
 
V-to-I Converter......................................................................... 14
 
Mixers .......................................................................................... 14
 
Emitter Follower Buffers ........................................................... 14
 
Bias Circuitry .............................................................................. 14
 
Register Structure....................................................................... 14
 
LO Divider Programming......................................................... 21
 
Programming Example.............................................................. 21
 
Applications Information .............................................................. 22
 
Basic Connections...................................................................... 22
 
Supply Connections ................................................................... 22
 
Synthesizer Connections ........................................................... 22
 
I/Q Output Connections ........................................................... 23
 
RF Input Connections ............................................................... 23
 
Charge Pump/VTUNE Connections ...................................... 23
 
LO Select Interface ..................................................................... 23
 
External LO Interface ................................................................ 23
 
Setting the Frequency of the PLL ............................................. 23
 
Register Programming............................................................... 23
 
EVM Measurements .................................................................. 24
 
Evaluation Board Layout and Thermal Grounding................... 25
 
ADRF6806 Software .................................................................. 30
 
Characterization Setups................................................................. 32
 
Outline Dimensions ....................................................................... 36
 
Ordering Guide .......................................................................... 36
 
REVISION HISTORY
3/12—Rev. A to Rev. B
Changes to Phase Noise—Using 67 kHz Loop Filter Parameter,
Table 1; Added Phase Noise—Using 2.5 kHz Loop Filter
Parameter, Table 1; Added PLL Figure of Merit (FOM)
Parameter, Table 1 ........................................................................ 4
Changes to Figure 21 and Figure 24 to Figure 26....................... 12
Changes to Figure 34...................................................................... 16
Changes to Figure 37...................................................................... 18
Changes to Figure 38...................................................................... 19
Changes to Figure 39...................................................................... 20
Changes to EVM Measurements Section and Figure 42,
Deleted Figure 43; Renumbered Sequentially ........................ 24
Changes to Figure 43...................................................................... 25
Added Figure 44.............................................................................. 26
Changes to Figure 46 and Figure 47............................................. 27
Changes to Table 7.......................................................................... 29
Changes to Figure 48...................................................................... 30
Changes to Figure 49...................................................................... 31
6/11—Rev. Sp0 to Rev. A



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