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OMAP3530ECBC 数据表(PDF) 202 Page - Texas Instruments |
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OMAP3530ECBC 数据表(HTML) 202 Page - Texas Instruments |
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202 / 264 page  OMAP3530/25 Applications Processor SPRS507F – FEBRUARY 2008 – REVISED OCTOBER 2009 www.ti.com Table 6-43. McBSP Output Clock Pulse Duration (continued) NO. PARAMETER OPP3 OPP2 UNIT MIN MAX MIN MAX Outputs tw(CLKH) Typical pulse duration, mcbsp1_clkr / mcbspx_clkx high(2) 0.5*P(1) 0.5*P(1) ns tw(CLKL) Typical pulse duration, mcbsp1_clkr / mcbspx_clkx low(2) 0.5*P(1) 0.5*P(1) ns tdc(CLK) Duty cycle error, mcbsp1_clkr / mcbspx_clkx(2) –0.75 0.75 –0.75 0.75 ns (1) P = mcbsp1_clkr / mcbspx_clkx clock period. (2) In mcbspx, x identifies the McBSP number: 1, 2, 3, 4, or 5. 6.6.1.1.1 Receive Timing with Rising Edge as Activation Edge Table 6-44 through Table 6-49 assume testing over the recommended operating conditions (see Figure 6-33 through Figure 6-34). Table 6-44. McBSP1, 2, and 3 (Sets #2 and #3) Timing Requirements – Rising Edge and Receive Mode(1) NO. PARAMETER 1.15 V 1.0 V UNIT MIN MAX MIN MAX B3 tsu(DRV-CLKAE) Setup time, mcbspx_dr valid before mcbsp1_clkr / Master 3.5 7.7 ns mcbspx_clkx active edge Slave 3.7 7.9 ns B4 th(CLKAE-DRV) Hold time, mcbspx_dr valid after mcbsp1_clkr / Master 1 1 ns mcbspx_clkx active edge Slave 0.4 0.4 ns B5 tsu(FSV-CLKAE) Setup time, mcbsp1_fsr / mcbspx_fsx valid before mcbsp1_clkr / 3.7 7.9 ns mcbspx_clkx active edge B6 th(CLKAE-FSV) Hold time, mcbsp1_fsr / mcbspx_fsx valid after mcbsp1_clkr / 0.5 0.5 ns mcbspx_clkx active edge (1) In mcbspx, x identifies the McBSP number: 1, 2, or 3. Note that for the McBSP3, these timings concern only Set #2 (multiplexing mode on UART pins) and Set #3 (multiplexing mode on McBSP1 pins). Table 6-45. McBSP1, 2, and 3 (Sets #2 and #3) Switching Characteristics – Rising Edge and Receive Mode(1) NO. PARAMETER 1.15 V 1.0 V UNIT MIN MAX MIN MAX B2 td(CLKAE-FSV) Delay time, mcbsp1_clkr / mcbspx_clkx active edge to mcbsp1_fsr / 0.7 14.8 0.7 29.6 ns mcbspx_fsx valid (1) In mcbspx, x identifies the McBSP number: 1, 2, or 3. Note that for the McBSP3, these timings concern only Set #2 (multiplexing mode on UART pins) and Set #3 (multiplexing mode on McBSP1 pins). Table 6-46. McBSP4 (Set #1) Timing Requirements – Rising Edge and Receive Mode(1) NO. PARAMETER 1.15 V 1.0 V UNIT MIN MAX MIN MAX B3 tsu(DRV-CLKXAE) Setup time, mcbspx_dr valid before Master 2.7 7.7 ns mcbspx_clkx active edge Slave 3.7 7.9 ns B4 th(CLKXAE-DRV) Hold time, mcbspx_dr valid after mcbspx_clkx Master 1 1 ns active edge Slave 0.4 0.4 ns B5 tsu(FSXV-CLKXAE) Setup time mcbspx_fsx valid before mcbspx_clkx active edge 3.7 7.9 ns B6 th(CLKXAE-FSXV) Hold Time mcbspx_fsx valid after mcbspx_clkx active edge 0.5 0.5 ns (1) In mcbspx, x identifies the McBSP number: 4. Note that for the McBSP4, these timings concern only Set #1: multiplexing mode by default. The McBSP4 is also multiplexed on GPMC pins (Set #2): the corresponding timings are specified in Table 6-48 and Table 6-49 TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 202 Submit Documentation Feedback |
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