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OMAP3530ECBC 数据表(PDF) 203 Page - Texas Instruments |
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OMAP3530ECBC 数据表(HTML) 203 Page - Texas Instruments |
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203 / 264 page  mcbspx_clkr mcbspx_fsr mcbspx_dr D7 D6 D5 B2 B2 B3 B4 030-068 mcbspx_clkr mcbspx_fsr mcbspx_dr D7 D6 D5 B3 B4 B5 B6 030-069 OMAP3530/25 Applications Processor www.ti.com SPRS507F – FEBRUARY 2008 – REVISED OCTOBER 2009 Table 6-47. McBSP4 (Set #1) Switching Characteristics – Rising Edge and Receive Mode(1) NO. PARAMETER 1.15 V 1.0 V UNIT MIN MAX MIN MAX B2 td(CLKXAE-FSXV) Delay time, mcbspx_clkx active edge to mcbspx_fsx valid 0.7 16.6 0.7 33.1 ns (1) In mcbspx, x identifies the McBSP number: 4. Note that for the McBSP4, these timings concern only Set #1: multiplexing mode by default. The McBSP4 is also multiplexed on GPMC pins (Set #2): the corresponding timings are specified in Table 6-48 and Table 6-49 Table 6-48. McBSP3 (Set #1), 4 (Set #2), and 5 Timing Requirements – Rising Edge and Receive Mode(1) NO. PARAMETER 1.15 V 1.0 V UNIT MIN MAX MIN MAX B3 tsu(DRV-CLKXAE) Setup time, mcbspx_dr valid before Master 5.6 12 ns mcbspx_clkx active edge Slave 5.8 12.2 ns B4 th(CLKXAE-DRV) Hold time, mcbspx_dr valid after mcbspx_clkx Master 1 1 ns active edge Slave 0.4 0.4 ns B5 tsu(FSXV-CLKXAE) Setup time, mcbspx_fsx valid before mcbspx_clkx active edge 5.8 12.2 ns B6 th(CLKXAE-FSXV) Hold time, mcbspx_fsx valid after mcbspx_clkx active edge 0.5 0.5 ns (1) In mcbspx, x identifies the McBSP number: 3, 4, or 5. Note that for the McBSP3, these timings concern only Set #1: multiplexing mode by default. The McBSP3 is also multiplexed on UART pins (Set #2) and on McBSP1 pins (Set #3): the corresponding timings are specified in Table 6-46 and Table 6-47. For the McBSP4, these timings concern only Set #2 (multiplexing mode on GPMC pins). Table 6-49. McBSP3 (Set #1), 4 (Set #2), and 5 Switching Requirements – Rising Edge and Receive Mode(1) NO. PARAMETER 1.15 V 1.0 V UNIT MIN MAX MIN MAX B2 td(CLKXAE-FSXV) Delay time, mcbspx_clkx active edge to mcbspx_fsx valid 0.7 22.2 0.7 44.4 ns Figure 6-33. McBSP Rising Edge Receive Timing in Master Mode Figure 6-34. McBSP Rising Edge Receive Timing in Slave Mode (1) In mcbspx, x identifies the McBSP number: 3, 4, or 5. Note that for the McBSP3, these timings concern only Set #1: multiplexing mode by default. The McBSP3 is also multiplexed on UART pins (Set #2) and on McBSP1 pins (Set #3): the corresponding timings are specified in Table 6-46 and Table 6-47. For the McBSP4, these timings concern only Set #2 (multiplexing mode on GPMC pins). Submit Documentation Feedback TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 203 |
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