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OMAP3530ECBC 数据表(PDF) 205 Page - Texas Instruments |
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OMAP3530ECBC 数据表(HTML) 205 Page - Texas Instruments |
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205 / 264 page  mcbspx_clkx mcbspx_fsx mcbspx_dx D7 D6 D5 B2 B2 B8 030-070 mcbspx_clkx mcbspx_fsx mcbspx_dx D7 D6 D5 B8 B5 B6 030-071 OMAP3530/25 Applications Processor www.ti.com SPRS507F – FEBRUARY 2008 – REVISED OCTOBER 2009 Table 6-54. McBSP3 (Set #1), 4 (Set #2), and 5 Timing Requirements – Rising Edge and Transmit Mode (continued) NO. PARAMETER 1.15 V 1.0 V UNIT MIN MAX MIN MAX B6 th(CLKXAE-FSXV) Hold time, mcbspx_fsx valid after mcbspx_clkx active 0.5 0.5 ns edge Table 6-55. McBSP 3 (Set #1), 4 (Set #2), and 5 Switching Requirements – Rising Edge and Transmit Mode(1) NO. PARAMETER 1.15 V 1.0 V UNIT MIN MAX MIN MAX B2 td(CLKXAE-FSXV) Delay time, mcbspx_clkx active edge to mcbspx_fsx 0.7 22.2 0.7 44.4 ns valid B8 td(CLKXAE-DXV) Delay time, mcbspx_clkx active edge to Master 0.6 22.2 0.6 44.4 ns mcbspx_dx valid Slave 0.6 22.2 0.6 44.4 ns Figure 6-35. McBSP Rising Edge Transmit Timing in Master Mode Figure 6-36. McBSP Rising Edge Transmit Timing in Slave Mode (1) In mcbspx, x identifies the McBSP number: 3, 4 or 5. Note that for the McBSP3, these timings concern only Set #1: multiplexing mode by default. The McBSP3 is also multiplexed on UART pins (Set #2) and on McBSP1 pins (Set #3): the corresponding timings are specified in the table above. For the McBSP4, these timings concern only Set #2 (multiplexing mode on GPMC pins). 6.6.1.1.3 Receive Timing with Falling Edge as Activation Edge Table 6-56 through Table 6-61 assume testing over the recommended operating conditions (see Figure 6-37 and Figure 6-38). Table 6-56. McBSP1, 2, and 3 (Sets #2 and #3) Timing Requirements – Falling Edge and Receive Mode(1) NO. PARAMETER 1.15 V 1.0 V UNIT MIN MAX MIN MAX B3 tsu(DRV-CLKAE) Setup time, mcbspx_dr valid before Master 3.5 7.7 ns mcbsp1_clkr / mcbspx_clkx active edge Slave 3.7 7.9 ns B4 th(CLKAE-DRV) Hold time, mcbspx_dr valid after Master 1 1 ns mcbsp1_clkr / mcbspx_clkx active edge Slave 0.4 0.4 ns B5 tsu(FSV-CLKAE) Setup time, mcbsp1_fsr / mcbspx_fsx valid before 3.7 7.9 ns mcbsp1_clkr /mcbspx_clkx active edge (1) In mcbspx, x identifies the McBSP number: 1, 2, or 3. Note that for the McBSP3, these timings concern only Set #2 (multiplexing mode on UART pins) and Set #3 (multiplexing mode on McBSP1 pins). Submit Documentation Feedback TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 205 |
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