OMAP3530ECBC datasheet(229/264 Pages) TI1

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6.6.5.2 I2C High-Speed Mode

i2cX_sda

i2cX_scl

STOP

START REPEAT

030-094

OMAP3530/25 Applications Processor

www.ti.com

SPRS507F – FEBRUARY 2008 – REVISED OCTOBER 2009

Table 6-108. I2C HighSpeed Mode Timings(1)(2)

NO.

PARAMETER

CB = 100 pF MAX

CB = 400 pF MAX

UNIT

MIN

MAX

MIN

MAX

fSCL

Clock frequency, i2cX_scl

3.4

1.7

MHz

tw(SCLH)

Pulse duration, i2cX_scl high

60(3)

120(3)

µs

tw(SCLL)

Pulse duration, i2cX_scl low

160(3)

320(3)

µs

tsu(SDAV-SCLH)

Setup time, i2cX_sda valid before i2cX_scl

active level

th(SCLH–SDAV)

Hold time, i2cX_sda valid after i2cX_scl active

0(2)

150

µs

level

tsu(SDAL-SCLH)

Setup time, i2cX_scl high after i2cX_sda low

160

µs

(for a START(4) condition or a repeated START

condition)

th(SCLH–SDAH)

Hold time, i2cX_sda low level after i2cX_scl high

160

µs

level (STOP condition)

th(SCLH–RSTART)

Hold time, i2cX_sda low level after i2cX_scl high

160

level (for a repeated START condition)

tR(SCL)

Rise time, i2cX_scl

tR(SCL)

Rise time, i2cX_scl after a repeated START

160

condition and after a bit acknowledge

tF(SCL)

Fall time, i2cX_scl

tR(SDA)

Rise time, i2cX_sda

160

tF(SDA)

Fall time, i2cX_sda

160

Capacitive load for each bus line

60(5)

(1)

In i2cX, X is equal to 1, 2, 3, or 4. Note that I2C4 is master transmitter only.

(2)

The device provides (via the I2C bus) a hold time of at least 300 ns for the i2cx_sda signal (refer to the fall and rise time of i2cx_scl) to

bridge the undefined region of the falling edge of i2cx_scl.

(3)

HS-mode master devices generate a serial clock signal with a high to low ratio of 1 to 2. tw(SCLL) > 2 × tw(SCLH).

(4)

After this time, the first clock is generated.

(5)

Maximum reference load for i2c4_scl and i2c4_sda is CB = 15 pF.

Figure 6-54. I2C – High-Speed Mode(1)(2)(3)

(1) HS-mode master devices generate a serial clock signal with a high-to-low ratio of 1 to 2. tw(SCLL) > 2 x tw(SCLH).

(2) In i2cX, X is equal to 1, 2, 3, or 4. Note that I2C4 is master transmitter only.

(3) After this time, the first clock is generated.

Table 6-109. Correspondence Standard vs. TI Timing References

TI-OMAP

STANDARD-I2C

S/F Mode

HS Mode

fSCL

FSCL

FSCLH

tw(SCLH)

THIGH

tw(SCLL)

TLOW

tsu(SDAV-SCLH)

TSU;DAT

th(SCLH-SDAV)

TSU;DAT

tsu(SDAL-SCLH)

TSU;STA

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