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OMAP3530ECBC 数据表(PDF) 225 Page - Texas Instruments |
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OMAP3530ECBC 数据表(HTML) 225 Page - Texas Instruments |
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225 / 264 page  hsusbx_tll_clk hsusbx_tll_stp hsusbx_tll_dir_&_nxt hsusbx_tll_data[7:0] Data_IN Data_OUT HSU0 HSU6 HSU2 HSU3 HSU5 HSU4 HSU7 HSU7 HSU6 030-088 6.6.4.4 High-Speed Universal Serial Bus (USB) on Ports 1, 2, and 3 – 8-bit TLL Master Mode OMAP3530/25 Applications Processor www.ti.com SPRS507F – FEBRUARY 2008 – REVISED OCTOBER 2009 Table 6-103. High-Speed USB Switching Characteristics – 12-bit TLL Master Mode (continued) NO. PARAMETER 1.15 V UNIT MIN MAX tj(CLK) Jitter standard deviation(2), hsusbx_tll_clk 200 ps HSU6 td(CLKL-DIRV) Delay time, hsusbx_tll_clk high to output hsusbx_tll_dir valid 9 ns td(CLKL-DIRIV) Delay time, hsusbx_tll_clk high to output hsusbx_tll_dir invalid 0 ns td(CLKL-NXTV) Delay time, hsusbx_tll_clk high to output hsusbx_tll_nxt valid 9 ns td(CLKL-NXTIV) Delay time, hsusbx_tll_clk high to output hsusbx_tll_nxt invalid 0 ns HSU7 td(CLKL-DV) Delay time, hsusbx_tll_clk high to output hsusbx_tll_data[7:0] valid 9 ns td(CLKL-DIV) Delay time, hsusbx_tll_clk high to output hsusbx_tll_data[7:0] invalid 0 ns tR(do) Rise time, output signals 2 ns tF(do) Fall time, output signals 2 ns (2) The jitter probability density can be approximated by a Gaussian function. In hsusbx, x is equal to 1, 2, or 3. Figure 6-51. High-Speed USB – 12-bit TLL Master Mode Table 6-105 and Table 6-106 assume testing over the recommended operating conditions (see Figure 6-52). Table 6-104. High-Speed USB Timing Conditions – 8-bit TLL Master Mode TIMING CONDITION PARAMETER VALUE UNIT Input Conditions tR Input signal rise time 2 ns tF Input signal fall time 2 ns Output Conditions CLOAD Output load capacitance 3 pF Table 6-105. High-Speed USB Timing Requirements – 8-bit TLL Master Mode(1) NO. PARAMETER 1.15 V UNIT MIN MAX HSU2 ts(STPV-CLKH) Setup time, hsusbx_tll_stp valid before hsusbx_tll_clk rising edge 6 ns HSU3 ts(CLKH-STPIV) Hold time, hsusbx_tll_stp valid after hsusbx_tll_clk rising edge 0 ns HSU4 ts(DATAV-CLKH) Setup time, hsusbx_tll_data[3:0] valid before hsusbx_tll_clk rising edge 3 ns (1) In hsusbx, x is equal to 1, 2, or 3. Submit Documentation Feedback TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 225 |
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