OMAP3530ECBC datasheet(222/264 Pages) TI1

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6.6.4.1 High-Speed Universal Serial Bus (USB) on Port 0 – 12-bit Slave Mode

OMAP3530/25 Applications Processor

SPRS507F – FEBRUARY 2008 – REVISED OCTOBER 2009

www.ti.com

–

8-bit TLL master mode (DDR)

• Port 3:

–

12-bit TLL master mode (SDR)

–

8-bit TLL master mode (DDR)

Table 6-96 and Table 6-97 assume testing over the recommended operating conditions (see Figure 6-49).

Table 6-95. High-Speed USB Timing Conditions – 12-bit Slave Mode

TIMING CONDITION PARAMETER

VALUE

UNIT

Input Conditions

Input Signal Rising Time

2.00

Input Signal Falling Time

2.00

Output Conditions

Cload

Output Load Capacitance

3.50

Table 6-96. High-Speed USB Timing Requirements – 12-bit Slave Mode(1)

NO.

PARAMETER

1.15 V

UNIT

MIN

MAX

HSU0

fp(CLK)

hsusb0_clk clock frequency(2)(3)

60.03

MHz

tj(CLK)

Cycle Jitter(3), hsusb0_clk

500.00

HSU3

ts(DIRV-CLKH)

Setup time, hsusb0_dir valid before hsusb0_clk rising edge

6.7

ts(NXTV-CLKH)

Setup time, hsusb0_nxt valid before hsusb0_clk rising edge

6.7

HSU4

th(CLKH-DIRIV)

Hold time, hsusb0_dir valid after hsusb0_clk rising edge

0.0

th(CLKH-NXT/IV)

Hold time, hsusb0_nxt valid after hsusb0_clk rising edge

0.0

HSU5

ts(DATAV-CLKH)

Setup time, hsusb0_data[0:7] valid before hsusb0_clk rising edge

6.7

HSU6

th(CLKH-DATIV)

Hold time, hsusb0_data[0:7] valid after hsusb0_clk rising edge

0.0

(1)

The timing requirements are assured for the cycle jitter error condition specified.

(2)

Related with the input maximum frequency supported by the I/F module.

(3)

Maximum cycle jitter supported by clk input clock.

Table 6-97. High-Speed USB Switching Characteristics – 12-bit Slave Mode

NO.

PARAMETER

1.15 V

UNIT

MIN

MAX

HSU1

td(clkL-STPV)

Delay time, hsusb0_clk high to output usb0_stp valid

9.0

td(clkL-STPIV)

Delay time, hsusb0_clk high to output usb0_stp invalid

0.5

HSU2

td(clkL-DV)

Delay time, hsusb0_clk high to output hsusb0_data[0:7] valid

9.0

td(clkL-DIV)

Delay time, hsusb0_clk high to output hsusb0_data[0:7] invalid

0.5

tr(do)

Rising time, output signals

2.0

tf(do)

Falling time, output signals

2.0

TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS

222

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