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STM32F372VB 数据表(PDF) 94 Page - STMicroelectronics |
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STM32F372VB 数据表(HTML) 94 Page - STMicroelectronics |
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94 / 128 page ![]() Electrical characteristics STM32F37x 94/128 Doc ID 022691 Rev 3 Table 59. I2S characteristics Symbol Parameter Conditions Min Max Unit DuCy(SCK)(1) I2S slave input clock duty cycle Slave mode 30 70 % fCK (1) 1/tc(CK) I2S clock frequency Master mode (data: 16 bits, Audio frequency = 48 kHz) 1.528 1.539 MHz Slave mode 0 12.288 tr(CK) (1) tf(CK) I2S clock rise and fall time Capacitive load CL =30pF 8 ns tv(WS) (1) WS valid time Master mode 4 th(WS) (1) WS hold time Master mode 4 tsu(WS) (1) WS setup time Slave mode 2 th(WS) (1) WS hold time Slave mode tw(CKH) (1) I2S clock high time Master fPCLK= 16 MHz, audio frequency = 48 kHz 306 tw(CKL) (1) I2S clock low time 312 tsu(SD_MR) (1) Data input setup time Master receiver 6 tsu(SD_SR) (1) Slave receiver 3 th(SD_MR) (1) Data input hold time Master receiver 1.5 th(SD_SR) (1) Slave receiver 1.5 tv(SD_ST) (1) Data output valid time Slave transmitter (after enable edge) 16 th(SD_ST) (1) Data output hold time Slave transmitter (after enable edge) 16 tv(SD_MT) (1) Data output valid time Master transmitter (after enable edge) 2 th(SD_MT) (1) Data output hold time Master transmitter (after enable edge) 0 1. Data based on design simulation, not tested in production. |
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