STM32F372VB datasheet(99/128 Pages) STMICROELECTRONICS

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STM32F37x

Electrical characteristics

Doc ID 022691 Rev 3

99/128

6.3.18

DAC electrical specifications

Table 63.

DAC characteristics

Symbol

Parameter

Min

Typ

Max

Unit

Comments

VDDA

Analog supply voltage

2.4

3.6

VREF+

Reference supply voltage

2.4

3.6

VREF+ must always be below VDDA

VSSA

Ground

RLOAD

(1)

Resistive load with buffer ON



(1)

Impedance output with buffer

OFF



When the buffer is OFF, the Minimum

resistive load between DAC_OUT

and VSS to have a 1% accuracy is

1.5 M



CLOAD

(1)

Capacitive load

Maximum capacitive load at

DAC_OUT pin (when the buffer is

ON).

DAC_OUT

min(1)

Lower DAC_OUT voltage

with buffer ON

0.2

It gives the maximum output

excursion of the DAC.

It corresponds to 12-bit input code

(0x0E0) to (0xF1C) at VREF+ = 3.6 V

and (0x155) and (0xEAB) at VREF+ =

2.4 V

DAC_OUT

max(1)

Higher DAC_OUT voltage

with buffer ON

VDDA – 0.2

DAC_OUT

min(1)

Lower DAC_OUT voltage

with buffer OFF

-0.5

It gives the maximum output

excursion of the DAC.

DAC_OUT

max(1)

Higher DAC_OUT voltage

with buffer OFF

-VREF+ – 1LSB V

IDDVREF+

(3)

DAC DC current

consumption in quiescent

mode (Standby mode)

220

µA

With no load, worst code (0xF1C) at

VREF+ = 3.6 V in terms of DC

consumption on the inputs

IDDA

(3)

DAC DC current

consumption in quiescent

mode(2)

380

µA

With no load, middle code (0x800) on

the inputs

480

µA

With no load, worst code (0xF1C) at

VREF+ = 3.6 V in terms of DC

consumption on the inputs

DNL(3)

Differential non linearity

Difference between two

consecutive code-1LSB)

±0.5

LSB

Given for the DAC in 10-bit

configuration

-±2

LSB

Given for the DAC in 12-bit

configuration

INL(3)

Integral non linearity

(difference between

measured value at Code i

and the value at Code i on a

line drawn between Code 0

and last Code 1023)

±1

LSB

Given for the DAC in 10-bit

configuration

±4

LSB

Given for the DAC in 12-bit

configuration

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