STM32F373VC datasheet(83/128 Pages) STMICROELECTRONICS

83 / 128 page

STM32F37x

Electrical characteristics

Doc ID 022691 Rev 3

83/128

Note:

I/O pins are powered from VDD voltage except pins which can be used as SDADC inputs:

- PB2, PB10 and PE7 to PE15 I/O pins are powered from VDDSD12.

- PB14 to PB15 and PD8 to PD15 I/O pins are powered from VDDSD3. All I/O pin ground is

internally connected to VSS.

VDD mentioned in the Table 52 represents power voltage for a given I/O pin (VDD or

VDDSD12 or VDDSD3).

All I/Os are CMOS and TTL compliant (no software configuration required). Their

characteristics cover more than the strict CMOS-technology or TTL parameters. The

coverage of these requirements is shown in Figure 17 and Figure 18 for standard I/Os, and

in Figure 19 and Figure 20 for 5 V tolerant I/Os.

Figure 17.

TC and TTa I/O input characteristics - CMOS port

Figure 18.

TC and TTa I/O input characteristics - TTL port

MS30255V2

VDD (V)

VIHmin 2.0

VILmax 0.7

VIL/VIH (V)

1.3

2.0

3.6

VILmax

= 0.3V

+0.07

0.6

2.7

3.0

3.3

CMOS standard requirements VILmax = 0.3VDD

VIHmin

= 0.445V

+0.398

Area not determined

Tested

in production

Tested

in production

Based

on design

simulations

Based

on design

simulations

CMOS

standard

requirements

VIHmin

= 0.7

VDD

VDD (V)

VIHmin 2.0

VILmax 0.7

VIL/VIH (V)

1.3

2.0

3.6

VILmax

= 0.3V

+ 0.07

0.8

2.7

3.0

3.3

VIHmin

= 0.445V

+0.398

Area not determined

Based

on design

simulations

Based

on design

simulations

TTL standard requirements VIHmin = 2 V

TTL standard requirements VILmax = 0.8 V

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