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STM32F373VC 数据表(PDF) 89 Page - STMicroelectronics |
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STM32F373VC 数据表(HTML) 89 Page - STMicroelectronics |
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89 / 128 page  STM32F37x Electrical characteristics Doc ID 022691 Rev 3 89/128 6.3.16 Communications interfaces I 2C interface characteristics Unless otherwise specified, the parameters given in Table 56 are derived from tests performed under ambient temperature, fPCLK1 frequency and VDD supply voltage conditions summarized in Table 22. The I 2C interface meets the requirements of the standard I2C communication protocol with the following restrictions: the I/O pins SDA and SCL are mapped to are not “true” open- drain. When configured as open-drain, the PMOS connected between the I/O pin and VDD is disabled, but is still present. The I 2C characteristics are described in Table 56. Refer also to Section 6.3.14: I/O port characteristics for more details on the input/output alternate function characteristics (SDA and SCL). Table 56. I2C characteristics(1) Symbol Parameter Standard mode Fast mode Fast mode Plus Unit Min Max Min Max Min Max tw(SCLL) SCL clock low time 4.7 1.3 0.5 µs tw(SCLH) SCL clock high time 4.0 0.6 0.26 tsu(SDA) SDA setup time 250 100 50 ns th(SDA) SDA data hold time 0(2) 3450(3) 0(2) 900(3) 0(4) 450(3) tr(SDA) tr(SCL) SDA and SCL rise time 1000 300 120 tf(SDA) tf(SCL) SDA and SCL fall time 300 300 120 th(STA) Start condition hold time 4.0 0.6 0.26 µs tsu(STA) Repeated Start condition setup time 4.7 0.6 0.26 tsu(STO) Stop condition setup time 4.0 0.6 0.26 s tw(STO:STA) Stop to Start condition time (bus free) 4.7 1.3 0.5 s Cb Capacitive load for each bus line 400 400 550 pF 1. The I2C characteristics are the requirements from I2C bus specification rev03. They are guaranteed by design when I2Cx_TIMING register is correctly programmed (Refer to reference manual). These characteristics are not tested in production. 2. The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL. 3. The maximum Data hold time has only to be met if the interface does not stretch the low period of SCL signal. 4. The device must internally provide a hold time of at least 120ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL. |
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