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STM8S003F3U6CTR 数据表(PDF) 35 Page - STMicroelectronics |
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STM8S003F3U6CTR 数据表(HTML) 35 Page - STMicroelectronics |
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35 / 100 page  Reset status Register name Register label Block Address Reserved 0x00 5342 0x00 TIM4 interrupt enable register TIM4_IER 0x00 5343 0x00 TIM4 status register TIM4_SR 0x00 5344 0x00 TIM4 event generation register TIM4_EGR 0x00 5345 0x00 TIM4 counter TIM4_CNTR 0x00 5346 0x00 TIM4 prescaler register TIM4_PSCR 0x00 5347 0xFF TIM4 auto-reload register TIM4_ARR 0x00 5348 Reserved area (153 bytes) 0x00 5349 to 0x00 53DF 0x00 ADC data buffer registers ADC _DBxR ADC1 0x00 53E0 to 0x00 53F3 Reserved area (12 bytes) 0x00 53F4 to 0x00 53FF 0x00 ADC control/status register ADC _CSR ADC1 0x00 5400 0x00 ADC configuration register 1 ADC_CR1 0x00 5401 0x00 ADC configuration register 2 ADC_CR2 0x00 5402 0x00 ADC configuration register 3 ADC_CR3 0x00 5403 0xXX ADC data register high ADC_DRH 0x00 5404 0xXX ADC data register low ADC_DRL 0x00 5405 0x00 ADC Schmitt trigger disable register high ADC_TDRH 0x00 5406 0x00 ADC Schmitt trigger disable register low ADC_TDRL 0x00 5407 35/100 DocID018576 Rev 3 Memory and register map STM8S003K3 STM8S003F3 |
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