MPC8315CVRADDA datasheet(73/106 Pages) FREESCALE

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MPC8315E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2

Freescale Semiconductor

SPI

21.1

SPI DC Electrical Characteristics

This table provides the DC electrical characteristics for the SPI.

21.2

SPI AC Timing Specifications

This table and provide the SPI input and output AC timing specifications.

This figure provides the AC test load for the SPI.

Figure 56. SPI AC Test Load

Figure 57 and Figure 58 represent the AC timing from Table 67. Note that although the specifications

generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge

is the active edge.

Table 66. SPI DC Electrical Characteristics

Characteristic

Symbol

Condition

Min

Max

Unit

Input high voltage

VIH

—

2.1

NVDD + 0.3

Input low voltage

VIL

—–0.3

0.8

Input current

IIN

——

±5

A

Output high voltage

VOH

IOH = –8.0 mA

2.4

—

Output low voltage

VOL

IOL = 8.0 mA

—

0.5

Output low voltage

VOL

IOL = 3.2 mA

—

0.4

Table 67. SPI AC Timing Specifications 1

Characteristic

Symbol 2

Min

Max

Unit

SPI outputs valid—master mode (internal clock) delay

tNIKHOV

—6

SPI outputs hold—master mode (internal clock) delay

tNIKHOX

0.5

SPI outputs valid—slave mode (external clock) delay

tNEKHOV

—8.5

SPI outputs hold—slave mode (external clock) delay

tNEKHOX

2—

SPI inputs—master mode (internal clock) input setup time

tNIIVKH

6—

SPI inputs—master mode (internal clock)input hold time

tNIIXKH

0—

SPI inputs—slave mode (external clock) input setup time

tNEIVKH

4—

SPI inputs—slave mode (external clock) input hold time

tNEIXKH

2—

Note:

1. Output specifications are measured from the 50% level of the rising edge of SPICLK to the 50% level of the signal. Timings

are measured at the pin.

2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for

inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tNIKHOX symbolizes the internal

timing (NI) for the time SPICLK clock reference (K) goes to the high state (H) until outputs (O) are invalid (X).

Output

Z0 = 50 

NVDD/2

RL = 50 

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