LSM303DLH datasheet(25/47 Pages) STMICROELECTRONICS

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LSM303DLH

Digital interfaces

Doc ID 16941 Rev 1

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7.1.2

Linear acceleration digital interface

For linear acceleration, the default (factory) 7-bit slave address is 001100xb. The

SDO/SA0 pad can be used to modify the least significant bit of the device address. If the

SA0 pad is connected to voltage supply, LSb is ‘1’ (address 0011001b) otherwise if the SA0

pad is connected to ground, LSb value is ‘0’ (address 0011000b). This solution permits

connecting and addressing two different accelerometers to the same I2C lines.

The slave address is completed with a read/write bit. If the bit was ‘1’ (read), a repeated

START (SR) condition will have to be issued after the two sub-address bytes; if the bit is ‘0’

(write) the master transmits to the slave with direction unchanged.

Table 14 explains how

the SAD+Read/Write bit pattern is composed, listing all the possible configurations.

Table 14.

SAD+Read/Write patterns

In order to read multiple bytes, it is necessary to assert the most significant bit of the sub-

address field. In other words, SUB(7) must be equal to 1 while SUB(6-0) represents the

address of the first register to be read.

In the presented communication format , MAK is Master Acknowledge and NMAK is No

Master Acknowledge.

7.1.3

Magnetic field digital interface

The system communicates via a two-wire I2C bus system as a slave device. The interface

protocol is defined by the I2C bus specification. The data rate is the standard mode 100

kbps or 400 kbps rates as defined by the I2C bus specifications. The bus bit format is an 8-

bit data/address send and a 1-bit acknowledge bit. The format of the data bytes (payload)

shall be case-sensitive ASCII characters or binary data to the magnetic sensor slave, and

binary data returned. Negative binary values will be in two’s complement form.

For magnetic sensor, the default (factory) 7-bit slave address is 0011110b

(0x3C) for write operations, or 00111101b (0x3D) for read operations.

The Serial Clock (SCL_M) and Serial Data (SDA_M) lines have optional internal pull-up

resistors, but require resistive pull-up (Rp) between the master device (usually a host

microprocessor) and the LSM303DLH. Pull-up resistance values of about 10 k

Ω are

recommended with a nominal 1.8 V digital supply voltage (Vdd_dig_M).

Command

SAD[6:1]

SAD[0] = SA0

R/W

SAD+R/W

Read

001100

00110001 (31h)

Write

001100

00110000 (30h)

Read

001100

00110011 (33h)

Write

001100

00110010 (32h)

Table 15.

Transfer when master is receiving (reading) multiple bytes of data from slave

Master

SAD

SUB

SAD

MAK

NMAK

Slave

SAK

DATA

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