LSM303DLH datasheet(26/47 Pages) STMICROELECTRONICS

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Digital interfaces

LSM303DLH

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Doc ID 16941 Rev 1

The SCL_M and SDA_M lines in this bus specification can be connected to a host of

devices. The bus can be a single master to multiple slaves, or it can be a multiple master

configuration. All data transfers are initiated by the master device which is responsible for

generating the clock signal, and the data transfers are 8 bits long. All devices are addressed

by the unique 7-bit address of the I2C. After each 8-bit transfer, the master device generates

a 9th clock pulse, and releases the SDA_M line.

The receiving device (addressed slave) pulls the SDA_M line low to acknowledge (ACK) the

successful transfer, or leaves the SDA_M high to negative acknowledge (NACK). As per the

I2C specification, all transitions in the SDA_M line must occur when SCL_M is low. This

requirement leads to two unique conditions on the bus associated with the SDA_M

transitions when SCL_M is high. The master device pulling the SDA line low while the

SCL_M line is high indicates the Start (S) condition, while the Stop (P) condition is indicated

by the SDA_M line pulled high while the SCL_M line is high. The I2C protocol also allows for

the Restart condition, in which the master device issues a second start condition without

issuing a stop.

All bus transactions begin with the master device issuing the start sequence followed by the

slave address byte. The address byte contains the slave address; the upper 7 bits (bits7-1),

and the least significant bit (LSb). The LSb of the address byte designates if the operation is

a read (LSb=1) or a write (LSb=0). At the 9th clock pulse, the receiving slave device issues

the ACK (or NACK). Following these bus events, the master sends data bytes for a write

operation, or the slave clocks out data with a read operation. All bus transactions are

terminated with the master issuing a stop sequence.

I2C bus control can be implemented with either hardware logic or in software. Typical

hardware designs release the SDA_M and SCL_M lines as appropriate to allow the slave

device to manipulate these lines. In a software implementation, care must be taken to

perform these tasks in code.

Magnetic signal interface reading/writing

The interface uses an address pointer to indicate which register location is to be read from

or written to. These pointer locations are sent from the master to this slave device and

succeed the 7-bit address plus 1 bit read/write identifier.

To minimize the communication between the master and magnetic digital interface of the

LSM303DLH, the address pointer is updated automatically without master intervention.

This automatic address pointer update has two additional features. First, when address 12

or higher is accessed the pointer updates to address 00, and secondly when address 09 is

reached, the pointer rolls back to address 03. Logically, the address pointer operation

functions as shown below.

●

if address pointer = 09, then address pointer = 03

●

while if address pointer >12, then address pointer = 0

●

while address pointer = address pointer + 1

●

the address pointer value itself cannot be read via the I2C bus.

Any attempt to read an invalid address location returns 0’s, and any write to an invalid

address location or an undefined bit within a valid address location is ignored by this device.

Table 16.

SAD+Read/Write patterns

Command

SAD[6:0]

R/W

SAD+R/W

Read

0011110

00111101 (3Dh)

Write

0011110

00111100 (3Ch)

Obsolete

Product(s)

- Obsolete

Product(s)

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