LSM303DLH datasheet(30/47 Pages) STMICROELECTRONICS

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Registers description

LSM303DLH

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Doc ID 16941 Rev 1

9.1.2

CTRL_REG2_A (21h)

The BOOT bit is used to refresh the content of internal registers stored in the Flash memory

block. At device power-up, the content of the Flash memory block is transferred to the

Low-power

0.5

Low-power

Table 21.

Normal-mode output data rate configurations and low-pass cut-off

frequencies

DR1

DR0

Output data rate [Hz]

ODR

Low-pass filter cut-off

frequency [Hz]

100

400

292

1000

780

Table 20.

Power mode and low-power output data rate configurations (continued)

PM2

PM1

PM0

Power mode selection

Output data rate [Hz]

ODRLP

Table 22.

CTRL_REG2_A register

BOOT

HPM1

HPM0

FDS

HPen2

HPen1

HPCF1

HPCF0

Table 23.

CTRL_REG2_A description

BOOT

Reboot memory content. Default value: 0

(0: normal mode; 1: reboot memory content)

HPM1, HPM0

High-pass filter mode selection. Default value: 00

(00: normal mode; Others: refer to

Table 24)

FDS

Filtered data selection. Default value: 0

(0: internal filter bypassed; 1: data from internal filter sent to output register)

HPen2

High-pass filter enabled for interrupt 2 source. Default value: 0

(0: filter bypassed; 1: filter enabled)

HPen1

High-pass filter enabled for interrupt 1 source. Default value: 0

(0: filter bypassed; 1: filter enabled)

HPCF1,

HPCF0

High-pass filter cut-off frequency configuration. Default value: 00

(00: HPc=8; 01: HPc=16; 10: HPc=32; 11: HPc=64)

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