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ADuCM361BCPZ128-R7 数据表(PDF) 9 Page - Analog Devices

部件名 ADuCM361BCPZ128-R7
功能描述  Low Power, Precision Analog Microcontroller with Dual Sigma-Delta ADCs, ARM Cortex-M3
PDF  24 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADuCM361BCPZ128-R7 数据表(HTML) 9 Page - Analog Devices

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Data Sheet
ADuCM360/ADuCM361
Rev. B | Page 9 of 24
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
Logic Outputs
Output High Voltage, VOH
ISOURCE = 1 mA
IOVDD − 0.4
V
Output Low Voltage, VOL
ISINK = 1 mA
0.4
V
CRYSTAL OSCILLATOR1
32.768 kHz crystal inputs
Logic Inputs, XTALI Only14
Input Low Voltage, VINL
0.8
V
Input High Voltage, VINH
1.7
V
XTALI Capacitance
6
pF
XTALO Capacitance
6
pF
ON-CHIP LOW POWER OSCILLATOR
Oscillator Frequency
32.768
kHz
Accuracy
−30
±10
+30
%
ON-CHIP HIGH FREQUENCY OSCILLATOR
Oscillator Frequency
16
MHz
Accuracy
−40°C to +125°C
−1.8
+1.4
%
Long Term Stability5
0.8
°C/1000Hr
PROCESSOR CLOCK RATE1
Nine programmable core clock
selections within specified range
0.0625
0.5
16
MHz
Using an External Clock
0.032768
16
MHz
PROCESSOR START-UP TIME1
At Power-On
Includes kernel power-on execution
time
41
ms
After Reset Event
Includes kernel power-on execution
time
1.44
ms
From Processor Power-Down
(Mode 1, Mode 2, and Mode 3)
fCLK is the Cortex-M3 core clock
3 to 5
fCLK
From Total Halt or Hibernate Mode
(Mode 4 or Mode 5)
30.8
μs
POWER REQUIREMENTS
Power Supply Voltages, VDD
AVDD, IOVDD
1.8
3.6
V
Power Consumption
IDD (MCU Active Mode)15, 16
Processor clock rate = 16 MHz;
all peripherals on (CLKSYSDIV = 0)
5.5
mA
Processor clock rate = 8 MHz;
all peripherals on (CLKSYSDIV = 1)
3
mA
Processor clock rate = 500 kHz; both
ADCs on (input buffers off) with PGA
gain = 4, 1 × SPI port on, all timers on
1
mA
IDD (MCU Powered Down)
Full temperature range, total halt mode
(Mode 4)
4
μA
Reduced temperature range, −40°C
to +85°C
4
μA
IDD, Total (ADC0)16
PGA enabled, gain ≥ 32
320
μA
PGA
Gain = 4, 8, or 16, PGA only
130
μA
Gain = 32, 64, or 128, PGA only
180
μA
Input Buffers
2 × input buffers = 70 μA
70
μA
Digital Interface and Modulator
70
μA
IDD (ADC1)
Input buffers off, gain = 4, 8, or 16 only
200
μA
External Reference Input Buffers
60 μA each
120
μA
1
These numbers are not production tested, but are guaranteed by design and/or characterization data at production release.
2
Tested at gain = 4 after initial offset calibration.
3
Measured with an internal short. A system zero-scale calibration removes this error.
4
A recalibration at any temperature removes these errors.
5
The long term stability specification is noncumulative. The drift in subsequent 1000 hour periods is significantly lower than in the first 1000 hour period.
6
These numbers do not include internal reference temperature drift.
7
Factory calibrated at gain = 1.



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