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ADuCM361BCPZ128-R7 数据表(PDF) 16 Page - Analog Devices |
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ADuCM361BCPZ128-R7 数据表(HTML) 16 Page - Analog Devices |
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16 / 24 page  ADuCM360/ADuCM361 Data Sheet Rev. B | Page 16 of 24 Table 13. SPI Slave Mode Timing Parameter Description Min Typ Max Unit t CS CS to SCLK edge 62.5 ns tSL SCLK low pulse width1 (SPIDIV + 1) × tUCLK ns tSH SCLK high pulse width1 62.5 (SPIDIV + 1) × tUCLK ns tDAV Data output valid after SCLK edge 49.1 ns tDSU Data input setup time before SCLK edge 20.2 ns tDHD Data input hold time after SCLK edge 10.1 ns tDF Data output fall time 12 35.5 ns tDR Data output rise time 12 35.5 ns tSR SCLK rise time 12 35.5 ns tSF SCLK fall time 12 35.5 ns tDOCS Data output valid after CS edge 25 ns tSFS CS high after SCLK edge 0 ns 1 tUCLK = 62.5 ns. It corresponds to the internal 16 MHz clock before the clock divider. SCLK (POLARITY = 0) CS SCLK (POLARITY = 1) tSH tSL tSR tSF tSFS MISO MSB BIT 6 TO BIT 1 LSB MOSI MSB IN BIT 6 TO BIT 1 LSB IN tDHD tDSU tDAV tDR tDF tCS Figure 6. SPI Slave Mode Timing (Phase Mode = 1) SCLK (POLARITY = 0) CS SCLK (POLARITY = 1) tSH tSL tSR tSF tSFS MISO MSB BIT 6 TO BIT 1 LSB MOSI MSB IN BIT 6 TO BIT 1 LSB IN tDHD tDSU tDAV tDR tDF tDOCS tCS Figure 7. SPI Slave Mode Timing (Phase Mode = 0) |
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