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ADuCM361BCPZ128-R7 数据表(PDF) 15 Page - Analog Devices

部件名 ADuCM361BCPZ128-R7
功能描述  Low Power, Precision Analog Microcontroller with Dual Sigma-Delta ADCs, ARM Cortex-M3
PDF  24 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADuCM361BCPZ128-R7 数据表(HTML) 15 Page - Analog Devices

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Data Sheet
ADuCM360/ADuCM361
Rev. B | Page 15 of 24
SPI TIMING SPECIFICATIONS
Table 12. SPI Master Mode Timing
Parameter
Description
Min
Typ
Max
Unit
tSL
SCLK low pulse width1
(SPIDIV + 1) × tUCLK
ns
tSH
SCLK high pulse width1
(SPIDIV + 1) × tUCLK
ns
tDAV
Data output valid after SCLK edge
0
35.5
ns
tDOSU
Data output setup time before SCLK edge1
(SPIDIV + 1) × tUCLK
ns
tDSU
Data input setup time before SCLK edge
58.7
ns
tDHD
Data input hold time after SCLK edge
16
ns
tDF
Data output fall time
12
35.5
ns
tDR
Data output rise time
12
35.5
ns
tSR
SCLK rise time
12
35.5
ns
tSF
SCLK fall time
12
35.5
ns
1 tUCLK = 62.5 ns. It corresponds to the internal 16 MHz clock before the clock divider.
SCLK
(POLARITY = 0)
CS
1/2 SCLK
CYCLE
SCLK
(POLARITY = 1)
MOSI
MSB
BIT 6 TO BIT 1
LSB
MISO
MSB IN
BIT 6 TO BIT 1
LSB IN
tSH
tCS
tSL
3/4 SCLK
CYCLE
tSFS
tSR
tSF
tDR
tDF
tDAV
tDSU
tDHD
Figure 4. SPI Master Mode Timing (Phase Mode = 1)
SCLK
(POLARITY = 0)
SCLK
(POLARITY = 1)
MOSI
MSB
BIT 6 TO BIT 1
LSB
MISO
MSB IN
BIT 6 TO BIT 1
LSB IN
tSH
tSR
tSF
tDR
tDF
tDAV
tDOSU
tDSU
tDHD
CS
1 SCLK CYCLE
tCS
tSL
1 SCLK CYCLE
t
SFS
Figure 5. SPI Master Mode Timing (Phase Mode = 0)



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