REV. B

–12–

AD8351

SINGLE-

ENDED

50

SOURCE

R1

50

100nF

25

100nF

AD8351

INHI

INLO

OPHI

OPLO

VOCM

25

25

DIGITAL

OUT

AD6645

AIN

AIN VREF

100nF

Figure 8. ADC Driving Application Using Single-Ended Input

ANALOG MULTIPLEXING

The AD8351 can be used as an analog multiplexer in applications

where it is desirable to select multiple high speed signals. The

isolation of each device when in a disabled state (PWUP pin pulled

low) is about 60 dBc for the maximum input level of 0.5 V p-p out

to 100 MHz. The low output noise spectral density allows for a

simple implementation as depicted in Figure 9. The PWUP inter-

face can be easily driven using most standard logic interfaces. By

using an N-bit digital interface, up to N devices can be controlled.

Output loading effects and noise need to be considered when using

a large number of input signal paths. Each disabled AD8351 pre-

sents approximately a 700

Ω load in parallel with the 150 Ω output

source impedance of the enabled device. As the load increases due

to the addition of N devices, the distortion performance will degrade

due to the heavier loading. Distortion better than –70 dBc can be

achieved with four devices muxed into a 1 k

Ω load for signal fre-

quencies up to 70 MHz.

AD8351

INHI

RGP1

RGP2

INLO

SIGNAL

INPUT 1

OPLO

OPHI

BIT 1

PWUP

AD8351

INHI

RGP1

RGP2

INLO

SIGNAL

INPUT 2

OPLO

OPHI

BIT 2

PWUP

AD8351

INHI

RGP1

RGP2

INLO

SIGNAL

INPUT N

OPLO

OPHI

BIT N

PWUP

MUX

OUTPUT

LOAD

N-BIT

DIGITAL

INTERFACE

Figure 9. Using Several AD8351s to Form an

N-Channel Analog MUX

I/O CAPACITIVE LOADING

Input or output direct capacitive loading greater than a few pico-

farads can result in excessive peaking and/or oscillation outside

the pass band. This results from the package and bond wire induc-

tance resonating in parallel with the input/output capacitance of

the device and the associated coupling that results internally

through the ground inductance. For low resistive load or source

resistance, the effective Q is lower, and higher relative capaci-

tance termination(s) can be allowed before oscillation or excessive

peaking occurs. These effects can be eliminated by adding series

25

Ω is all that is required for I/O capacitive loading greater than

~2 pF. The higher the C, the smaller the R parasitic suppression

in-band peaking, especially for light resistive loads.

AD8351

1k

Figure 10. Input and Output Parasitic Suppression

Capacitive Loading Effects

values (low gain) cause high ac-peaking inside the pass band,

resulting in poor settling in the time domain. As an example,

when driving a 1 k

Ω (A

Figure 11. Reducing Gain Peaking with Parasitic