STM32F100C datasheet(69/98 Pages) STMICROELECTRONICS

69 / 98 page

STM32F100xC, STM32F100xD, STM32F100xE

Electrical characteristics

Doc ID 15081 Rev 7

69/98

5.3.14

I/O port characteristics

General input/output characteristics

Unless otherwise specified, the parameters given in Table 43 are derived from tests

performed under the conditions summarized in Table 9. All I/Os are CMOS and TTL

compliant.

All I/Os are CMOS and TTL compliant (no software configuration required). Their

characteristics cover more than the strict CMOS-technology or TTL parameters. The

coverage of these requirements is shown in Figure 23 and Figure 24 for standard I/Os, and

in Figure 25 and Figure 26 for 5 V tolerant I/Os.

Table 43.

I/O static characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VIL

Standard I/O input

low level voltage

–0.3

0.28*(VDD–2 V)+0.8 V

I/O FT(1) input low

level voltage

–0.3

0.32*(VDD–2 V)+0.75 V

VIH

Standard I/O input

high level voltage

0.41*(VDD–2 V) +1.3 V

VDD+0.3

I/O FT(1) input high

level voltage

VDD > 2 V

0.42*(VDD–2)+1 V

5.5

VDD ≤2 V

5.2

Vhys

Standard I/O Schmitt

trigger voltage

hysteresis(2)

200

I/O FT Schmitt trigger

voltage hysteresis(2)

5% VDD

(3)

Ilkg

Input leakage

current(4)

VSS ≤VIN ≤VDD

Standard I/Os

±1

µA

VIN = 5 V

I/O FT

RPU

Weak pull-up

equivalent resistor(5)

VIN = VSS

RPD

Weak pull-down

equivalent resistor(5)

VIN = VDD

CIO

I/O pin capacitance

FT = 5V tolerant. To sustain a voltage higher than VDD+0.3 the internal pull-up/pull-down resistors must be disabled.

Hysteresis voltage between Schmitt trigger switching levels. Guaranteed by design, not tested in production.

With a minimum of 100 mV.

Leakage could be higher than max. if negative current is injected on adjacent pins.

Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This

PMOS/NMOS contribution to the series resistance is minimum (~10% order)

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