PCF8564AUSLASH5BBSLASH1 datasheet(25/48 Pages) NXP

25 / 48 page

PCF8564A

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Product data sheet

Rev. 3 — 26 August 2013

25 of 48

NXP Semiconductors

PCF8564A

Real time clock and calendar

10.3 Interface watchdog timer

During read/write operations, the time counting circuits are frozen. To prevent a situation

where the accessing device becomes locked and does not clear the interface, the

PCF8564A has a built in watchdog timer. Should the interface be active for more than 1 s

from the time a valid slave address is transmitted, then the PCF8564A will automatically

clear the interface and allow the time counting circuits to continue counting. The watchdog

will trigger between 1 s and 2 s after receiving a valid slave address. Each time the

watchdog period is exceeded, 1 s will be lost from the time counters.

The watchdog is implemented to prevent the excessive loss of time due to interface

access failure e.g. if main power is removed from a battery backed-up system during an

interface access.

a. Correct data transfer: read or write

b. Incorrect data transfer; read or write

Fig 19. Interface watchdog timer

PCF8564AU/5BB/1 数据表(PDF) 25 Page - NXP Semiconductors