PCF8564AUSLASH5BBSLASH1 datasheet(31/48 Pages) NXP

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PCF8564A

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Product data sheet

Rev. 3 — 26 August 2013

31 of 48

NXP Semiconductors

PCF8564A

Real time clock and calendar

15. Dynamic characteristics

[1]

Integrated load capacitance, CL(itg), is a calculation of COSCI and COSCO in series:

[2]

Unspecified for fCLKOUT = 32.768 kHz.

[3]

All timing values are valid within the operating supply voltage at ambient temperature and referenced to VIL and VIH with an input voltage

swing of VSS to VDD.

[4]

A detailed description of the I2C-bus specification is given in Ref. 9 “UM10204”.

Table 31.

Dynamic characteristics

VDD = 1.8 V to 5.5 V; VSS =0V; Tamb = 40 C to +85 C; fosc = 32.768 kHz; quartz Rs =40 k; CL = 8 pF; unless otherwise

specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Oscillator

CL(itg)

integrated load capacitance

[1] 68

f

osc/fosc

relative oscillator frequency

variation

V

DD =200 mV;

Tamb =25 C

-0.2

-ppm

Quartz crystal parameters

series resistance

100



load capacitance

CLKOUT output



CLKOUT

duty cycle on pin CLKOUT

[2] -50

I2C-bus timing characteristics (see Figure 25)[3][4]

fSCL

SCL clock frequency

400

kHz

tHD;STA

hold time (repeated) START

condition

0.6

s

tSU;STA

set-up time for a repeated START

condition

0.6

s

tLOW

LOW period of the SCL clock

1.3

s

tHIGH

HIGH period of the SCL clock

0.6

s

rise time of both SDA and SCL

signals

0.3

s

fall time of both SDA and SCL

signals

0.3

s

capacitive load for each bus line

400

tSU;DAT

data set-up time

100

tHD;DAT

data hold time

tSU;STO

set-up time for STOP condition

0.6

s

tw(spike)

spike pulse width

Litg



OSCI

OSCO





OSCI

OSCO



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