PCF8564AUSLASH5BBSLASH1 datasheet(4/48 Pages) NXP

4 / 48 page

PCF8564A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 26 August 2013

4 of 48

NXP Semiconductors

PCF8564A

Real time clock and calendar

Pinning information

7.1 Pinning

7.2 Pin description

[1]

The substrate (rear side of the die) is at VSS potential and must not be connected.

Viewed from active side. For mechanical details, see Figure 27 and Figure 28.

Fig 2.

Pinning diagram of PCF8564A

Table 4.

Pin description

Input or input/output pins must always be at a defined level (VSS or VDD) unless otherwise specified.

Symbol

Description

OSCI

oscillator input

OSCO

oscillator output

INT

interrupt output, open-drain, active LOW

VSS

ground[1]

SDA

serial data input and output

SCL

serial clock input

CLKOUT

clock output, push-pull

VDD

supply voltage

CLKOE

CLKOUT enable input

PCF8564AU/5BB/1 数据表(PDF) 4 Page - NXP Semiconductors

PCF8564AU/5BB/1 数据表(HTML) 4 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

数据表下载