AD9854AST datasheet(32/52 Pages) AD

32 / 52 page

AD9854

Rev. E | Page 32 of 52

PROGRAMMING THE AD9854

The AD9854 register layout table (Table 8) contains information

for programming the chip for the desired functionality. Although

many applications require very little programming to configure

the AD9854, some use all 12 accessible register banks. The

AD9854 supports an 8-bit parallel I/O operation or an SPI®-

compatible serial I/O operation. All accessible registers can be

written and read back in either I/O operating mode.

S/P SELECT (Pin 70) is used to configure the I/O mode.

Systems that use the parallel I/O mode must connect the S/P

SELECT pin to VDD. Systems that operate in the serial I/O mode

must tie the S/P SELECT pin to GND.

Regardless of the mode, the I/O port data is written to a buffer

memory and only affects operation of the part after the contents

of the buffer memory are transferred to the register banks. This

transfer of information occurs synchronously to the system

clock in one of two ways:

•

Internally, at a rate programmable by the user.

•

Externally, by the user. I/O operations can occur in the

absence of REFCLK, but the data cannot be moved from

the buffer memory to the register bank without REFCLK.

(See the Internal and External Update Clock section for

more details.)

MASTER RESET

The MASTER RESET pin must be held at logic high active

for a minimum of 10 system clock cycles. This initializes the

communications bus and loads the default values listed in the

Table 8 section.

Table 7. REFCLK Multiplier Control Register Values

Reference Multiplier

Multiplier Value

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

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