AD9854

Rev. E | Page 30 of 52

12-BIT DIGITAL

MULTIPLIER

12

12

(BYPASS MULTIPLIER)

OSK EN = 0

OSK EN = 1

OSK EN = 0

OSK EN = 1

12

12

DIGITAL

SIGNAL IN

USER-PROGRAMMABLE

12-BIT Q CHANNEL

MULTIPLIER

OUTPUT SHAPED

KEYING Q MULTIPLIER

REGISTER

12

OSK INT = 0

OSK INT = 0

1

8-BIT RAMP

RATE

COUNTER

SYSTEM

CLOCK

ON/OFF OUTPUT SHAPED

KEYING PIN

SINE DAC

12-BIT

UP/DOWN

COUNTER

DDS DIGITAL

OUTPUT

Figure 50. Block Diagram of Q DAC Pathway of the Digital Multiplier Section Responsible for the Output Shaped Keying Function

The two fixed elements of the transition time are the period of

the system clock (which drives the ramp rate counter) and the

number of amplitude steps (4096). For example, if the system

clock of the AD9854 is 100 MHz (10 ns period) and the ramp

rate counter is programmed for a minimum count of 3, the

transition takes two system clock periods (one rising edge loads

the countdown value, and the next edge decrements the counter

from 3 to 2). If the countdown value is less than 3, the ramp rate

counter stalls and therefore produces a constant scaling value to

the digital multipliers. This stall condition may have an application

for the user.

The relationship of the 8-bit countdown value to the time

between output pulses is given as

(N + 1) × System Clock Period

where N is the 8-bit countdown value.

It takes 4096 of these pulses to advance the 12-bit up-counter

from zero scale to full scale. Therefore, the minimum output

shaped keying ramp time for a 100 MHz system clock is

4096 × 4 × 10 ns ≈ 164 μs

The maximum ramp time is

4096 × 256 × 10 ns ≈ 10.5 ms

Finally, changing the logic state of Pin 30, output shaped keying

automatically performs the programmed output envelope functions

when OSK INT is high. A logic high on Pin 30 causes the outputs

to linearly ramp up to full-scale amplitude and to hold until the

logic level is changed to low, causing the outputs to ramp down

to zero scale.

I AND Q DACS

The sine and cosine outputs of the DDS drive the Q and I DACs,

respectively (300 MSPS maximum). The maximum amplitudes

are current-output DACs with a full-scale maximum output of

20 mA; however, a nominal 10 mA output current provides the

best spurious-free dynamic range (SFDR) performance. The value

compliance specifications limit the maximum voltage developed

at the outputs to −0.5 V to +1 V. Voltages developed beyond this

limitation cause excessive DAC distortion and possibly permanent

damage. The user must choose a proper load impedance to limit

the output voltage swing to the compliance limits. Both DAC

outputs should be terminated equally for best SFDR, especially

at higher output frequencies, where harmonic distortion errors

are more prominent.

Both DACs are preceded by inverse sin(x)/x filters (also called

inverse sinc filters) that precompensate for DAC output amplitude

variations over frequency to achieve flat amplitude response from

dc to Nyquist. Both DACs can be powered down when not needed

by setting the DAC PD bit high (Address 1D hex of the control

register). I DAC outputs are designated as IOUT1 and IOUT1,

Pin 48 and Pin 49, respectively. Q DAC outputs are designated

as IOUT2 and IOUT2, Pin 52 and Pin 51, respectively.

CONTROL DAC

The 12-bit Q DAC can be reconfigured to perform as a control

or auxiliary DAC. The control DAC output can provide dc

control levels to external circuitry, generate ac signals, or enable

duty cycle control of the on-board comparator. When the SRC

Q DAC bit in the control register (Parallel Address 1F hex) is

set high, the Q DAC inputs are switched from internal 12-bit

Q data source (default setting) to external 12-bit, twos complement

data supplied by the user. Data is channeled through the serial

or parallel interface to the 12-bit Q DAC register (Address 26 hex

and Address 27 hex) at a maximum data rate of 100 MHz. This

DAC is clocked at the system clock, 300 MSPS (maximum), and

has the same maximum output current capability as that of the I

output current for both DACs. When not needed, the control

DAC can be separately powered down to conserve power by

setting the Q DAC power-down bit high (Address 1D hex).

Control DAC outputs are designated as IOUT2 and IOUT2,

Pin 52 and Pin 51, respectively.