AD9854AST datasheet(18/52 Pages) AD

18 / 52 page

AD9854

Rev. E | Page 18 of 52

CLOCK OUT = 200MHz

LPF

SIN

LPF

AD9854

COS

REFERENCE

CLOCK

COMPARATORS

AOUT = 100MHz

Figure 33. Clock Frequency Doubler

µPROCESSOR/

CONTROLLER

FPGA, ETC.

RSET

8-BIT PARALLEL OR

SERIAL PROGRAMMING

DATA AND CONTROL

SIGNALS

AD9854

REFERENCE

CLOCK

300MHz MAX DIRECT

MODE OR 15MHz TO 75MHz

MAX IN THE 4× TO 20×

CLOCK

MULTIPLIER MODE

2kΩ

I DAC

Q DAC OR

CONTROL

DAC

LOW-PASS

FILTER

LOW-PASS

FILTER

NOTES

1. IOUT = APPROX 20mA MAX WHEN RSET = 2kΩ.

2. SWITCH POSITION 1 PROVIDES COMPLEMENTARY

SINUSOIDAL SIGNALS TO THE COMPARATOR

TO PRODUCE A FIXED 50% DUTY CYCLE FROM THE

COMPARATOR.

3. SWITCH POSITION 2 PROVIDES THE SAME DUTY CYCLE

USING QUADRATURE SINUSOIDAL SIGNALS TO THE

COMPARATOR OR A DC THRESHOLD VOLTAGE TO

ALLOW SETTING OF THE COMPARATOR DUTY CYCLE

(DEPENDS ON THE CONFIGURATION OF THE Q DAC).

CMOS LOGIC CLOCK OUT

Figure 34. Frequency Agile Clock Generator Applications for the AD9854

AD9854AST 数据表(PDF) 18 Page - Analog Devices

AD9854AST 数据表(HTML) 18 Page - Analog Devices

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