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AD9854

Rev. E | Page 31 of 52

INVERSE SINC FUNCTION

The inverse sinc function precompensates input data to both

DACs for the sin(x)/x roll-off characteristic inherent in the

DAC’s output spectrum. This allows wide bandwidth signals

(such as QPSK) to be output from the DACs without

appreciable amplitude variations as a function of frequency. The

inverse sinc function can be bypassed to reduce power

consumption significantly, especially at higher clock speeds.

When the Q DAC is configured as a control DAC, the inverse

sinc function does not apply to the Q path.

Inverse sinc is engaged by default and is bypassed by bringing

the bypass inverse sinc bit high in Control Register 20 hex, as

noted in Table 8.

FREQUENCY NORMALIZED TO SAMPLE RATE

4.0

00.1

–0.5

3.5

3.0

2.5

2.0

1.5

1.0

0.5

–1.0

–1.5

–2.0

–2.5

–3.0

–3.5

–4.0

0.2

0.3

0.4

0.5

SYSTEM

ISF

SINC

Figure 51. Inverse Sinc Filter Response

REFCLK MULTIPLIER

The REFCLK multiplier is a programmable PLL-based

reference clock multiplier that allows the user to select an

integer clock multiplying value over the range of 4× to 20×.

With this function, users can input as little as 15 MHz at the

REFCLK input to produce a 300 MHz internal system clock.

Five bits in Control Register 1E hex set the multiplier value, as

detailed in Table 7.

The REFCLK multiplier function can be bypassed to allow

direct clocking of the AD9854 from an external clock source.

The system clock for the AD9854 is either the output of the

REFCLK multiplier (if it is engaged) or the REFCLK inputs.

REFCLK can be either a single-ended or differential input by

setting Pin 64, DIFF CLK ENABLE, low or high, respectively.

PLL Range Bit

The PLL range bit selects the frequency range of the REFCLK

multiplier PLL. For operation from 200 MHz to 300 MHz

(internal system clock rate), the PLL range bit should be set to

Logic 1. For operation below 200 MHz, the PLL range bit

should be set to Logic 0. The PLL range bit adjusts the PLL loop

parameters for best phase noise performance within each range.

PLL Filter

The PLL FILTER pin (Pin 61) provides the connection for the

external zero-compensation network of the PLL loop filter. The

zero-compensation network consists of a 1.3 kΩ resistor in

series with a 0.01 μF capacitor. The other side of the network

should be connected as close as possible to Pin 60, AVDD. For

optimum phase noise performance, the clock multiplier can be

bypassed by setting the bypass PLL bit in Control Register

Address 1E hex.

Differential REFCLK Enable

A high level on the DIFF CLK ENABLE pin enables the differ-

ential clock inputs, REFCLK and REFCLK (Pin 69 and Pin 68,

respectively). The minimum differential signal amplitude required

is 400 mV p-p at the REFCLK input pins. The center point or

common-mode range of the differential signal can range from

1.6 V to 1.9 V.

When Pin 64 (DIFF CLK ENABLE) is tied low, REFCLK

(Pin 69) is the only active clock input. This is referred to as

single-ended mode. In this mode, Pin 68 (REFCLK) should

be tied low or high.

High Speed Comparator

The comparator is optimized for high speed and has a toggle rate

greater than 300 MHz, low jitter, sensitive input, and built-in

hysteresis. It also has an output level of 1 V p-p minimum into 50 Ω

or CMOS logic levels into high impedance loads. The comparator

can be powered down separately to conserve power. This com-

parator is used in clock-generator applications to square up the

filtered sine wave generated by the DDS.

Power-Down

The programming registers allow several individual stages to be

powered down to reduce power consumption while maintaining

the functionality of the desired stages. These stages are identified

in Table 8, Address 1D hex. Power-down is achieved by setting

the specified bits to logic high. A logic low indicates that the

stages are powered up.

Furthermore, and perhaps most significantly, the inverse sinc

filters and the digital multiplier stages can be bypassed to achieve

significant power reduction by programming the control registers

in Address 20 hex. Again, logic high causes the stage to be bypassed.

Of particular importance is the inverse sinc filter; this stage

consumes a significant amount of power.

A full power-down occurs when all four PD bits in Control

consumption to approximately 10 mW (3 mA).

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