EPF10K100 datasheet(8/128 Pages) ALTERA

8 / 128 page

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

The logic array consists of logic array blocks (LABs). Each LAB contains

eight LEs and a local interconnect. An LE consists of a 4-input look-up

table (LUT), a programmable flipflop, and dedicated signal paths for carry

and cascade functions. The eight LEs can be used to create medium-sized

blocks of logic—8-bit counters, address decoders, or state machines—or

combined across LABs to create larger logic blocks. Each LAB represents

about 96 usable gates of logic.

Signal interconnections within FLEX 10K devices and to and from device

pins are provided by the FastTrack Interconnect, a series of fast,

continuous row and column channels that run the entire length and width

of the device.

Each I/O pin is fed by an I/O element (IOE) located at the end of each row

and column of the FastTrack Interconnect. Each IOE contains a

bidirectional I/O buffer and a flipflop that can be used as either an output

or input register to feed input, output, or bidirectional signals. When used

with a dedicated clock pin, these registers provide exceptional

performance. As inputs, they provide setup times as low as 1.6 ns and

hold times of 0 ns; as outputs, these registers provide clock-to-output

times as low as 5.3 ns. IOEs provide a variety of features, such as JTAG

BST support, slew-rate control, tri-state buffers, and open-drain outputs.

Figure 1 shows a block diagram of the FLEX 10K architecture. Each group

of LEs is combined into an LAB; LABs are arranged into rows and

columns. Each row also contains a single EAB. The LABs and EABs are

interconnected by the FastTrack Interconnect. IOEs are located at the end

of each row and column of the FastTrack Interconnect.

EPF10K100 数据表(PDF) 8 Page - Altera Corporation