EPF10K100 datasheet(33/128 Pages) ALTERA

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Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Signals on the peripheral control bus can also drive the four global signals,

referred to as GLOBAL0 through GLOBAL3 in Tables 8 and 9. The

internally generated signal can drive the global signal, providing the same

low-skew, low-delay characteristics for an internally generated signal as

for a signal driven by an input. This feature is ideal for internally

generated clear or clock signals with high fan-out. When a global signal is

driven by internal logic, the dedicated input pin that drives that global

signal cannot be used. The dedicated input pin should be driven to a

known logic state (such as ground) and not be allowed to float.

When the chip-wide output enable pin is held low, it will tri-state all pins

on the device. This option can be set in the Global Project Device Options

menu. Additionally, the registers in the IOE can be reset by holding the

chip-wide reset pin low.

Row-to-IOE Connections

When an IOE is used as an input signal, it can drive two separate row

channels. The signal is accessible by all LEs within that row. When an IOE

is used as an output, the signal is driven by a multiplexer that selects a

signal from the row channels. Up to eight IOEs connect to each side of

each row channel. See Figure 14.

Figure 14. FLEX 10K Row-to-IOE Connections

Each IOE is driven by an

m-to-1 multiplexer.

Each IOE can drive up to two

row channels.

IOE8

IOE1

Row FastTrack

Interconnect

The values for m and n are provided in Table 10.

EPF10K100 数据表(PDF) 33 Page - Altera Corporation