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STM32L152C6 数据表(PDF) 81 Page - STMicroelectronics

部件名 STM32L152C6
功能描述  Ultra-low-power 32-bit MCU ARM-based Cortex-M3, 128KB Flash, 16KB SRAM, 4KB EEPROM, LCD, USB, ADC, DAC
PDF  121 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STM32L152C6 数据表(HTML) 81 Page - STMicroelectronics

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STM32L151x6/8/B, STM32L152x6/8/B
Electrical characteristics
Doc ID 17659 Rev 8
81/121
Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 18 and
Table 44, respectively.
Unless otherwise specified, the parameters given in Table 44 are derived from tests
performed under ambient temperature and VDD supply voltage conditions summarized in
Table 14.
Table 44.
I/O AC characteristics(1)
OSPEEDRx
[1:0] bit
value(1)
Symbol
Parameter
Conditions
Min
Max(2)
Unit
00
fmax(IO)out Maximum frequency
(3)
CL = 50 pF, VDD = 2.7 V to 3.6 V
-
400
kHz
CL = 50 pF, VDD = 1.65 V to 2.7 V
-
400
tf(IO)out
tr(IO)out
Output rise and fall time
CL = 50 pF, VDD = 2.7 V to 3.6 V
-
625
ns
CL = 50 pF, VDD = 1.65 V to 2.7 V
-
625
01
fmax(IO)out Maximum frequency
(3)
CL = 50 pF, VDD = 2.7 V to 3.6 V
-
2
MHz
CL = 50 pF, VDD = 1.65 V to 2.7 V
-
1
tf(IO)out
tr(IO)out
Output rise and fall time
CL = 50 pF, VDD = 2.7 V to 3.6 V
-
125
ns
CL = 50 pF, VDD = 1.65 V to 2.7 V
-
250
10
Fmax(IO)out Maximum frequency
(3)
CL = 50 pF, VDD = 2.7 V to 3.6 V
-
10
MHz
CL = 50 pF, VDD = 1.65 V to 2.7 V
-
2
tf(IO)out
tr(IO)out
Output rise and fall time
CL = 50 pF, VDD = 2.7 V to 3.6 V
-
25
ns
CL = 50 pF, VDD = 1.65 V to 2.7 V
-
125
11
Fmax(IO)out Maximum frequency
(3)
CL = 50 pF, VDD = 2.7 V to 3.6 V
-
50
MHz
CL = 50 pF, VDD = 1.65 V to 2.7 V
-
8
tf(IO)out
tr(IO)out
Output rise and fall time
CL = 30 pF, VDD = 2.7 V to 3.6 V
-
5
ns
CL = 50 pF, VDD = 1.65 V to 2.7 V
-
30
-tEXTIpw
Pulse width of external
signals detected by the
EXTI controller
8-
1.
The I/O speed is configured using the OSPEEDRx[1:0] bits. Refer to the STM32L15xxx reference manual for a description
of GPIO Port configuration register.
2.
Guaranteed by design. Not tested in production.
3.
The maximum frequency is defined in Figure 18.



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